# Library Script
#
# Created by Libedit V2.02
#
Set Wire_Bend 2;
Grid mm;
Edit STM32F40X_LQFP64.sym;
Pin 'VBAT' Pwr None Middle R0 Both 0 (-33.02 17.78);
Pin 'PC13' I/O None Middle R0 Both 0 (-33.02 15.24);
Pin 'PC14' I/O None Middle R0 Both 0 (-33.02 12.7);
Pin 'PC15' I/O None Middle R0 Both 0 (-33.02 10.16);
Pin 'PH0' I/O None Middle R0 Both 0 (-33.02 7.62);
Pin 'PH1' I/O None Middle R0 Both 0 (-33.02 5.08);
Pin 'NRST' In Dot Middle R0 Both 0 (-33.02 2.54);
Pin 'PC0' I/O None Middle R0 Both 0 (-33.02 0);
Pin 'PC1' I/O None Middle R0 Both 0 (-33.02 -2.54);
Pin 'PC2' I/O None Middle R0 Both 0 (-33.02 -5.08);
Pin 'PC3' I/O None Middle R0 Both 0 (-33.02 -7.62);
Pin 'VSSA' Pwr None Middle R0 Both 0 (-33.02 -10.16);
Pin 'VDDA' Pwr None Middle R0 Both 0 (-33.02 -12.7);
Pin 'PA0' I/O None Middle R0 Both 0 (-33.02 -15.24);
Pin 'PA1' I/O None Middle R0 Both 0 (-33.02 -17.78);
Pin 'PA2' I/O None Middle R0 Both 0 (-33.02 -20.32);
Pin 'PA3' I/O None Middle R90 Both 0 (-17.78 -35.56);
Pin 'VSS@18' Pwr None Middle R90 Both 0 (-15.24 -35.56);
Pin 'VDD@19' Pwr None Middle R90 Both 0 (-12.7 -35.56);
Pin 'PA4' I/O None Middle R90 Both 0 (-10.16 -35.56);
Pin 'PA5' I/O None Middle R90 Both 0 (-7.62 -35.56);
Pin 'PA6' I/O None Middle R90 Both 0 (-5.08 -35.56);
Pin 'PA7' I/O None Middle R90 Both 0 (-2.54 -35.56);
Pin 'PC4' I/O None Middle R90 Both 0 (0 -35.56);
Pin 'PC5' I/O None Middle R90 Both 0 (2.54 -35.56);
Pin 'PB0' I/O None Middle R90 Both 0 (5.08 -35.56);
Pin 'PB1' I/O None Middle R90 Both 0 (7.62 -35.56);
Pin 'PB2' I/O None Middle R90 Both 0 (10.16 -35.56);
Pin 'PB10' I/O None Middle R90 Both 0 (12.7 -35.56);
Pin 'PB11' I/O None Middle R90 Both 0 (15.24 -35.56);
Pin 'VCAP_1' Pas None Middle R90 Both 0 (17.78 -35.56);
Pin 'VDD@32' Pwr None Middle R90 Both 0 (20.32 -35.56);
Pin 'PB12' I/O None Middle R180 Both 0 (35.56 -20.32);
Pin 'PB13' I/O None Middle R180 Both 0 (35.56 -17.78);
Pin 'PB14' I/O None Middle R180 Both 0 (35.56 -15.24);
Pin 'PB15' I/O None Middle R180 Both 0 (35.56 -12.7);
Pin 'PC6' I/O None Middle R180 Both 0 (35.56 -10.16);
Pin 'PC7' I/O None Middle R180 Both 0 (35.56 -7.62);
Pin 'PC8' I/O None Middle R180 Both 0 (35.56 -5.08);
Pin 'PC9' I/O None Middle R180 Both 0 (35.56 -2.54);
Pin 'PA8' I/O None Middle R180 Both 0 (35.56 0);
Pin 'PA9' I/O None Middle R180 Both 0 (35.56 2.54);
Pin 'PA10' I/O None Middle R180 Both 0 (35.56 5.08);
Pin 'PA11' I/O None Middle R180 Both 0 (35.56 7.62);
Pin 'PA12' I/O None Middle R180 Both 0 (35.56 10.16);
Pin 'PA13' I/O None Middle R180 Both 0 (35.56 12.7);
Pin 'VCAP_2' Pas None Middle R180 Both 0 (35.56 15.24);
Pin 'VDD@48' Pwr None Middle R180 Both 0 (35.56 17.78);
Pin 'PA14' I/O None Middle R270 Both 0 (20.32 33.02);
Pin 'PA15' I/O None Middle R270 Both 0 (17.78 33.02);
Pin 'PC10' I/O None Middle R270 Both 0 (15.24 33.02);
Pin 'PC11' I/O None Middle R270 Both 0 (12.7 33.02);
Pin 'PC12' I/O None Middle R270 Both 0 (10.16 33.02);
Pin 'PD2' I/O None Middle R270 Both 0 (7.62 33.02);
Pin 'PB3' I/O None Middle R270 Both 0 (5.08 33.02);
Pin 'PB4' I/O None Middle R270 Both 0 (2.54 33.02);
Pin 'PB5' I/O None Middle R270 Both 0 (0 33.02);
Pin 'PB6' I/O None Middle R270 Both 0 (-2.54 33.02);
Pin 'PB7' I/O None Middle R270 Both 0 (-5.08 33.02);
Pin 'BOOT0' I/O None Middle R270 Both 0 (-7.62 33.02);
Pin 'PB8' I/O None Middle R270 Both 0 (-10.16 33.02);
Pin 'PB9' I/O None Middle R270 Both 0 (-12.7 33.02);
Pin 'VSS@63' Pwr None Middle R270 Both 0 (-15.24 33.02);
Pin 'VDD@64' Pwr None Middle R270 Both 0 (-17.78 33.02);
Layer 94;
Wire  0.254 (-25.4 27.94) (-27.94 25.4) (-27.94 -30.48) (30.48 -30.48) \
      (30.48 27.94) (-25.4 27.94);
Layer 95;
Change Size 2.1844;
Change Ratio 8;
Text '>NAME' MR0 (-27.94 30.48);
Layer 96;
Change Size 2.1844;
Change Ratio 8;
Text '>VALUE' MR0 (-27.94 27.94);

Edit LQFP64.pac;
Description '<strong>LQFP64</strong><br />';
Layer 1;
Smd '1' 1.2 0.24 -0 R90 (-3.75 -6);
Layer 1;
Smd '2' 1.2 0.24 -0 R90 (-3.25 -6);
Layer 1;
Smd '3' 1.2 0.24 -0 R90 (-2.75 -6);
Layer 1;
Smd '4' 1.2 0.24 -0 R90 (-2.25 -6);
Layer 1;
Smd '5' 1.2 0.24 -0 R90 (-1.75 -6);
Layer 1;
Smd '6' 1.2 0.24 -0 R90 (-1.25 -6);
Layer 1;
Smd '7' 1.2 0.24 -0 R90 (-0.75 -6);
Layer 1;
Smd '8' 1.2 0.24 -0 R90 (-0.25 -6);
Layer 1;
Smd '9' 1.2 0.24 -0 R90 (0.25 -6);
Layer 1;
Smd '10' 1.2 0.24 -0 R90 (0.75 -6);
Layer 1;
Smd '11' 1.2 0.24 -0 R90 (1.25 -6);
Layer 1;
Smd '12' 1.2 0.24 -0 R90 (1.75 -6);
Layer 1;
Smd '13' 1.2 0.24 -0 R90 (2.25 -6);
Layer 1;
Smd '14' 1.2 0.24 -0 R90 (2.75 -6);
Layer 1;
Smd '15' 1.2 0.24 -0 R90 (3.25 -6);
Layer 1;
Smd '16' 1.2 0.24 -0 R90 (3.75 -6);
Layer 1;
Smd '17' 1.2 0.24 -0 R180 (6 -3.75);
Layer 1;
Smd '18' 1.2 0.24 -0 R180 (6 -3.25);
Layer 1;
Smd '19' 1.2 0.24 -0 R180 (6 -2.75);
Layer 1;
Smd '20' 1.2 0.24 -0 R180 (6 -2.25);
Layer 1;
Smd '21' 1.2 0.24 -0 R180 (6 -1.75);
Layer 1;
Smd '22' 1.2 0.24 -0 R180 (6 -1.25);
Layer 1;
Smd '23' 1.2 0.24 -0 R180 (6 -0.75);
Layer 1;
Smd '24' 1.2 0.24 -0 R180 (6 -0.25);
Layer 1;
Smd '25' 1.2 0.24 -0 R180 (6 0.25);
Layer 1;
Smd '26' 1.2 0.24 -0 R180 (6 0.75);
Layer 1;
Smd '27' 1.2 0.24 -0 R180 (6 1.25);
Layer 1;
Smd '28' 1.2 0.24 -0 R180 (6 1.75);
Layer 1;
Smd '29' 1.2 0.24 -0 R180 (6 2.25);
Layer 1;
Smd '30' 1.2 0.24 -0 R180 (6 2.75);
Layer 1;
Smd '31' 1.2 0.24 -0 R180 (6 3.25);
Layer 1;
Smd '32' 1.2 0.24 -0 R180 (6 3.75);
Layer 1;
Smd '33' 1.2 0.24 -0 R270 (3.75 6);
Layer 1;
Smd '34' 1.2 0.24 -0 R270 (3.25 6);
Layer 1;
Smd '35' 1.2 0.24 -0 R270 (2.75 6);
Layer 1;
Smd '36' 1.2 0.24 -0 R270 (2.25 6);
Layer 1;
Smd '37' 1.2 0.24 -0 R270 (1.75 6);
Layer 1;
Smd '38' 1.2 0.24 -0 R270 (1.25 6);
Layer 1;
Smd '39' 1.2 0.24 -0 R270 (0.75 6);
Layer 1;
Smd '40' 1.2 0.24 -0 R270 (0.25 6);
Layer 1;
Smd '41' 1.2 0.24 -0 R270 (-0.25 6);
Layer 1;
Smd '42' 1.2 0.24 -0 R270 (-0.75 6);
Layer 1;
Smd '43' 1.2 0.24 -0 R270 (-1.25 6);
Layer 1;
Smd '44' 1.2 0.24 -0 R270 (-1.75 6);
Layer 1;
Smd '45' 1.2 0.24 -0 R270 (-2.25 6);
Layer 1;
Smd '46' 1.2 0.24 -0 R270 (-2.75 6);
Layer 1;
Smd '47' 1.2 0.24 -0 R270 (-3.25 6);
Layer 1;
Smd '48' 1.2 0.24 -0 R270 (-3.75 6);
Layer 1;
Smd '49' 1.2 0.24 -0 R0 (-6 3.75);
Layer 1;
Smd '50' 1.2 0.24 -0 R0 (-6 3.25);
Layer 1;
Smd '51' 1.2 0.24 -0 R0 (-6 2.75);
Layer 1;
Smd '52' 1.2 0.24 -0 R0 (-6 2.25);
Layer 1;
Smd '53' 1.2 0.24 -0 R0 (-6 1.75);
Layer 1;
Smd '54' 1.2 0.24 -0 R0 (-6 1.25);
Layer 1;
Smd '55' 1.2 0.24 -0 R0 (-6 0.75);
Layer 1;
Smd '56' 1.2 0.24 -0 R0 (-6 0.25);
Layer 1;
Smd '57' 1.2 0.24 -0 R0 (-6 -0.25);
Layer 1;
Smd '58' 1.2 0.24 -0 R0 (-6 -0.75);
Layer 1;
Smd '59' 1.2 0.24 -0 R0 (-6 -1.25);
Layer 1;
Smd '60' 1.2 0.24 -0 R0 (-6 -1.75);
Layer 1;
Smd '61' 1.2 0.24 -0 R0 (-6 -2.25);
Layer 1;
Smd '62' 1.2 0.24 -0 R0 (-6 -2.75);
Layer 1;
Smd '63' 1.2 0.24 -0 R0 (-6 -3.25);
Layer 1;
Smd '64' 1.2 0.24 -0 R0 (-6 -3.75);
Layer 21;
Wire  0.254 (-5 5) (5 5) (5 -5) (-4 -5);
Wire  0.254 (-5 -4) (-5 5);
Wire  0.254 (-5 -4) (-4 -5);
Layer 25;
Change Size 1.016;
Change Ratio 25;
Text '>NAME' R0 (-7 5.5);
Layer 25;
Change Size 1.016;
Change Ratio 25;
Text '>VALUE' R0 (-4 3);

Edit STM32F405R*T.dev;
Prefix 'IC';
Description '\
<strong>STM32F405R*T</strong><br/>\n\
ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, 17 TIMs, 3 ADCs, 15 comm.';
Value Off;
Add STM32F40X_LQFP64 'G$1' Next 0 (0 0);
Package 'LQFP64' '''''';
Technology -'' 'G';
Connect  'G$1.VBAT' '1'  'G$1.PC13' '2'  'G$1.PC14' '3'  'G$1.PC15' '4'  'G$1.PH0' '5' \
         'G$1.PH1' '6'  'G$1.NRST' '7'  'G$1.PC0' '8'  'G$1.PC1' '9'  'G$1.PC2' '10'  'G$1.PC3' '11' \
         'G$1.VSSA' '12'  'G$1.VDDA' '13'  'G$1.PA0' '14'  'G$1.PA1' '15'  'G$1.PA2' '16'  'G$1.PA3' '17' \
         'G$1.VSS@18' '18'  'G$1.VDD@19' '19'  'G$1.PA4' '20'  'G$1.PA5' '21'  'G$1.PA6' '22'  'G$1.PA7' '23' \
         'G$1.PC4' '24'  'G$1.PC5' '25'  'G$1.PB0' '26'  'G$1.PB1' '27'  'G$1.PB2' '28'  'G$1.PB10' '29' \
         'G$1.PB11' '30'  'G$1.VCAP_1' '31'  'G$1.VDD@32' '32'  'G$1.PB12' '33'  'G$1.PB13' '34'  'G$1.PB14' '35' \
         'G$1.PB15' '36'  'G$1.PC6' '37'  'G$1.PC7' '38'  'G$1.PC8' '39'  'G$1.PC9' '40'  'G$1.PA8' '41' \
         'G$1.PA9' '42'  'G$1.PA10' '43'  'G$1.PA11' '44'  'G$1.PA12' '45'  'G$1.PA13' '46'  'G$1.VCAP_2' '47' \
         'G$1.VDD@48' '48'  'G$1.PA14' '49'  'G$1.PA15' '50'  'G$1.PC10' '51'  'G$1.PC11' '52'  'G$1.PC12' '53' \
         'G$1.PD2' '54'  'G$1.PB3' '55'  'G$1.PB4' '56'  'G$1.PB5' '57'  'G$1.PB6' '58'  'G$1.PB7' '59' \
         'G$1.BOOT0' '60'  'G$1.PB8' '61'  'G$1.PB9' '62'  'G$1.VSS@63' '63'  'G$1.VDD@64' '64';
Grid inch;
