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-- Company: 
-- Engineer:
--
-- Create Date:   18:06:40 11/23/2006
-- Design Name:   INDOOR2
-- Module Name:   C:/Tools/FPGA/Xilinx/my_project/multi_function_timer/indoor2_test.vhd
-- Project Name:  indoor2
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: MFT
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
use IEEE.STD_LOGIC_ARITH.ALL;
USE ieee.numeric_std.ALL;

ENTITY INDOOR2_test is
END INDOOR2_test;

ARCHITECTURE behavior OF INDOOR2_test is

	-- Component Declaration for the Unit Under Test (UUT)
	component Indoor2 is
		port (
				clk : in std_logic;
				pulse_in : in std_logic_vector(0 to 7);
				pulse_to_cpu : out std_logic_vector(0 to 1);
				pulse_from_cpu : in std_logic;
				out_addr : in std_logic_vector(0 to 2);
				pulse_out : out std_logic_vector(0 to 7)
			);
	end component;

	--Inputs
	signal clk :  std_logic := '0';
	signal pulse_in : std_logic_vector(0 to 7) := "00000000";
	signal pulse_from_cpu : std_logic := '0';
	signal out_addr : std_logic_vector(0 to 2) := "000";

	--Outputs
	
	signal i : integer := 0;
BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: INDOOR2 PORT MAP(
		clk => clk,
		pulse_in => pulse_in,
		pulse_from_cpu => pulse_from_cpu,
		out_addr => out_addr
	);

	tb : process
	begin
	
		-- Wait 100 ns for global reset to finish
		wait for 100 ns;
		
		-- Place stimulus here
		wait for 100 ns;

		clk <= '1';
		while true loop
			clk <= not clk;
			if clk = '1' then
				case i mod (20ms / (50ns * 2))  is
					when 0 => pulse_in(0) <= '1';
					when 15000 => pulse_in(0 to 1) <= "01";
					when 30000 => pulse_in(1 to 2) <= "01";
					when 45000 => pulse_in(2 to 3) <= "01";
					when 60000 => pulse_in(3 to 4) <= "01";
					when 75000 => pulse_in(4) <= '0';
					when others => pulse_in(0 to 4) <= pulse_in(0 to 4);
				end case;
				
				case i mod (12ms / (50ns * 2)) is
					when 10000 => pulse_in(5) <= '1';
					when 15000 => pulse_in(7) <= '1';
					when 17500 => pulse_in(6) <= '1';
					when 22500 => pulse_in(6) <= '0';
					when 25000 => pulse_in(5) <= '0'; pulse_in(7) <= '0';
					when others => pulse_in(5 to 7) <= pulse_in(5 to 7);
				end case;
				
				case i mod (20ms / (50ns * 2)) is
					when 350 => pulse_from_cpu <= '1';
					when 650 => pulse_from_cpu <= '0';
					when others => pulse_from_cpu <= pulse_from_cpu;
				end case;
				
				i <= i + 1;
				
				if i mod (2ms / (50ns * 2)) = 0 then
					if out_addr > 7 then
						out_addr <= "000";
					else
						out_addr <= out_addr + 1;
					end if;
				end if;
			end if;
			wait for 50 ns;
		end loop;

		wait; -- will wait forever
	END PROCESS;

END;