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-- Company: 
-- Engineer: 
-- 
-- Create Date:    00:00:37 12/14/2006 
-- Design Name: 
-- Module Name:    indoor2 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity Divider10 is 
	port (
			clk_in : in std_logic;
			clk_out : out std_logic
		);
end Divider10;

architecture Behavioral of Divider10 is
	signal timer : std_logic_vector(2 downto 0)
		:= conv_std_logic_vector(0, 3);
	signal high : boolean := false;
begin
	clk_out <= '1' when high else '0';
	process(clk_in) begin
		if clk_in'event and clk_in = '1' then
			if timer > 4 then
				timer <= conv_std_logic_vector(0, 3);
				high <= not high;
			else
				timer <= timer + 1;
				high <= high;
			end if;
		end if;
	end process;
end Behavioral;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity PulseRepeater is
	generic (
			BIT_WIDTH : positive := 8
		);
	port (
			clk : in std_logic;
			tick : in std_logic;
			sync : in std_logic;
			wire_in : in std_logic;
			wire_out : out std_logic
		);
end PulseRepeater;

architecture Behavioral of PulseRepeater is
	signal timer : std_logic_vector(BIT_WIDTH - 1 downto 0)
		:= conv_std_logic_vector(0, BIT_WIDTH);
	type state_type is (READY, LOADING, LOADED, LOADING_RUNNING, RUNNING);
	signal current_state : state_type := READY;
	signal next_state : state_type;
	signal sync_fallen : boolean;
	signal wire_in_risen : boolean;
begin
	wire_out <= '1' 
			when (current_state = LOADING_RUNNING or current_state = RUNNING)
		else '0';
	
	process(clk)
	begin
		if clk'event and clk = '1' then
			current_state <= next_state;
		end if;
	end process;
	
	process(tick)
	begin
		if tick'event and tick = '1' then
			case current_state is
				when LOADING => timer <= timer + 1;
				when RUNNING => timer <= timer - 1;
				when READY => timer <= (others => '0');
				when others => timer <= timer;
			end case;
		end if;
	end process;
	
	process(current_state, wire_in) begin
		if not (current_state = READY) then
			wire_in_risen <= false;
		elsif wire_in'event and wire_in = '1' then
			wire_in_risen <= true;
		end if;
	end process;
	
	process(current_state, sync) begin
		if not (current_state = LOADING or current_state = LOADED) then
			sync_fallen <= false;
		elsif sync'event and sync = '0' then
			sync_fallen <= true;
		end if;
	end process;
	
	process(current_state, sync_fallen, wire_in_risen, timer, wire_in)
	begin
		case current_state is
			when READY =>
				if wire_in_risen then
					next_state <= LOADING;
				else
					next_state <= READY;
				end if;
			when LOADING =>
				if sync_fallen then
					next_state <= LOADING_RUNNING;
				elsif wire_in = '0' then
					next_state <= LOADED;
				else
					next_state <= LOADING;
				end if;
			when LOADED =>
				if sync_fallen then
					next_state <= RUNNING;
				else
					next_state <= LOADED;
				end if;
			when LOADING_RUNNING =>
				if wire_in = '0' then
					next_state <= RUNNING;
				else
					next_state <= LOADING_RUNNING;
				end if;
			when RUNNING =>
				if timer = 0 then
					next_state <= READY;
				else
					next_state <= RUNNING;
				end if;
		end case;
	end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity PulseRepeaterArray is 
	generic(
			BIT_WIDTH : positive := 8;
			UNIT_NUMBER : positive := 1
		);
	port(
			clk : in std_logic;
			tick : in std_logic;
			sync : in std_logic;
			wire_in : in std_logic_vector(0 to UNIT_NUMBER - 1);
			wire_out : out std_logic_vector(0 to UNIT_NUMBER - 1)
		);
end PulseRepeaterArray;

architecture Behavioral of PulseRepeaterArray is
	component PulseRepeater is
		generic (
				BIT_WIDTH : positive := 8
			);
		port (
				clk : in std_logic;
				tick : in std_logic;
				sync : in std_logic;
				wire_in : in std_logic;
				wire_out : out std_logic
			);
	end component;
	signal buf_wire_in : std_logic_vector(0 to UNIT_NUMBER - 1);
	signal wire_out_internal : std_logic_vector(0 to UNIT_NUMBER - 1);
	signal sync_internal : std_logic_vector(0 to UNIT_NUMBER - 1);
begin
	process(clk)
	begin
		if clk'event and clk = '0' then
			buf_wire_in <= wire_in;
			sync_internal(0) <= sync;
		end if;
	end process;

	wire_out <= wire_out_internal;
	gen_PR : for i in 0 to UNIT_NUMBER - 1 generate
		gen_sync : if i > 0 generate
			sync_internal(i) <= wire_out_internal(i - 1);
		end generate;
		UNIT_PR : PulseRepeater
		generic map(BIT_WIDTH)
		port map(clk, tick, sync_internal(i), buf_wire_in(i), wire_out_internal(i));
	end generate;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity Decoder8 is 
	port (
			wire_in : in std_logic;
			addr : in std_logic_vector(2 downto 0);
			wire_out : out std_logic_vector(0 to 7)
		);
end Decoder8;

architecture Behavioral of Decoder8 is
	signal decoded_addr : integer range 0 to 7; 
begin
	decoded_addr <= conv_integer(addr);
	gen : for i in 0 to 7 generate
		wire_out(i) <= wire_in when decoded_addr = i else '0';
	end generate;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Indoor2 is
	port (
			clk : in std_logic;
			pulse_in : in std_logic_vector(0 to 7);
			pulse_to_cpu : out std_logic_vector(0 to 1);
			pulse_from_cpu : in std_logic;
			out_addr : in std_logic_vector(2 downto 0);
			pulse_out : out std_logic_vector(0 to 7)
		);
end Indoor2;

architecture Behavioral of Indoor2 is
	component Divider10 is 
		port (
				clk_in : in std_logic;
				clk_out : out std_logic
			);
	end component;
	component PulseRepeaterArray is 
		generic(
				BIT_WIDTH : positive := 8;
				UNIT_NUMBER : positive := 1
			);
		port(
				clk : in std_logic;
				tick : in std_logic;
				sync : in std_logic;
				wire_in : in std_logic_vector(0 to UNIT_NUMBER - 1);
				wire_out : out std_logic_vector(0 to UNIT_NUMBER - 1)
			);
	end component;
	component Decoder8 is 
		port (
				wire_in : in std_logic;
				addr : in std_logic_vector(2 downto 0);
				wire_out : out std_logic_vector(0 to 7)
			);
	end component;
	signal tick_internal : std_logic;
	constant PR_CHANNELS : positive := 3;
	constant PR_LSB : integer := 8 - PR_CHANNELS;
	signal pra_out : std_logic_vector(PR_LSB to 7);
	signal buf_pulse_to_cpu : std_logic_vector(0 to 7);
begin
	gen_pulse_to_cpu : for i in 0 to 7 generate
		gen_normal : if i < PR_LSB generate
			buf_pulse_to_cpu(i) <= pulse_in(i);
		end generate;
		gen_pra : if i >= PR_LSB generate
			buf_pulse_to_cpu(i) <= pra_out(i);
		end generate;
	end generate;
	
	Div : Divider10
		port map(clk, tick_internal);
	PRA : PulseRepeaterArray
		generic map(12, PR_CHANNELS)
		port map(
				clk, tick_internal,
				pulse_in(PR_LSB - 1), 
				pulse_in(PR_LSB to 7), 
				pra_out
			);
	pulse_to_cpu(0)
		<= buf_pulse_to_cpu(0) or
			buf_pulse_to_cpu(2) or
			buf_pulse_to_cpu(4) or
			buf_pulse_to_cpu(6);
	pulse_to_cpu(1)
		<= buf_pulse_to_cpu(1) or
			buf_pulse_to_cpu(3) or
			buf_pulse_to_cpu(5) or
			buf_pulse_to_cpu(7);
	Dec : Decoder8
		port map(pulse_from_cpu, out_addr, pulse_out);
end Behavioral;