library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity top is
  port (
      sysclk : in std_logic;
      mcu_tx0 : in std_logic;
      mcu_rx0 : out std_logic;
      slct : in std_logic_vector(3 downto 0);
      cmd : inout std_logic_vector(3 downto 0);
      cmd_drv1 : inout std_logic_vector(3 downto 0);
      cmd_drv2 : inout std_logic_vector(3 downto 0));
end top;

architecture Behavioral of top is
  signal por_counter : std_logic_vector(3 downto 0) := (others => '1');
  signal cmd_oe : std_logic_vector(3 downto 0);
begin
  process(mcu_tx0) begin
    if mcu_tx0'event and mcu_tx0 = '0' then
      if por_counter > conv_std_logic_vector(0, por_counter'length) then
        por_counter <= por_counter - 1;
      else
        por_counter <= por_counter;
      end if;
    end if;
  end process;

  gen_cmd: for i in 0 to 3 generate
    cmd_oe(i) <= '1' when (mcu_tx0 = '0' and slct(i) = '0') 
            or (por_counter > conv_std_logic_vector(0, por_counter'length))
        else '0';
    cmd(i) <= '0' when cmd_oe(i) = '1' else 'Z';
    cmd_drv1(i) <= '0' when cmd_oe(i) = '1' else 'Z';
    cmd_drv2(i) <= '0' when cmd_oe(i) = '1' else 'Z';
  end generate;
  
  mcu_rx0 <= '1' when cmd = (not conv_std_logic_vector(0, cmd'length))
      else '0';
end Behavioral;