library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity top is port ( -- Global gpio : inout std_logic_vector(7 downto 0); led : out std_logic_vector(1 downto 0); -- XBee xbee_dout : in std_logic; xbee_din : out std_logic; xbee_cts_n : in std_logic; xbee_rts_n : out std_logic; xbee_reset_n : out std_logic; xbee_rssi : in std_logic; xbee_on : in std_logic; -- CC2570 ant_reset_n : out std_logic; ant_txd_sout : in std_logic; ant_rxd_sin : out std_logic; ant_br2_sclk : inout std_logic; ant_br1_sflow : out std_logic; ant_br3_fspi : out std_logic; ant_rts_sen : in std_logic; ant_ee_cs : in std_logic; ant_ee_miso : out std_logic; ant_ee_mosi : in std_logic; ant_ee_clk : in std_logic; ant_sleep_mrdy_n : out std_logic; ant_suspend_n_srdy_n : out std_logic; ant_portsel : out std_logic ); end top; architecture Behavioral of top is signal sysclk : std_logic; signal clk_1 : std_logic; component ufm_pack port ( oscena : in std_logic; osc : out std_logic); end component; component DividerN is generic ( divide_value : positive := 8); port ( clk, reset : in std_logic; clk_out, tc : out std_logic); end component; begin ufm : ufm_pack port map ( oscena => '1', osc => sysclk); div1 : DividerN generic map ( divide_value => 4600000) -- –ñ4.6MHz => –ñ1Hz port map ( clk => sysclk, reset => '0', clk_out => clk_1); gpio(1) <= 'Z'; gpio(7 downto 2) <= (others => 'Z'); led(0) <= clk_1; led(1) <= not clk_1; -- XBee gpio(0) <= xbee_dout; xbee_din <= gpio(1); xbee_rts_n <= '0'; xbee_reset_n <= '1'; -- CC2570 ant_reset_n <= '1'; ant_rxd_sin <= '0'; ant_br2_sclk <= 'Z'; ant_br1_sflow <= '0'; ant_br3_fspi <= '0'; ant_ee_miso <= '0'; ant_sleep_mrdy_n <= '0'; ant_suspend_n_srdy_n <= '0'; ant_portsel <= '0'; end Behavioral;