-- megafunction wizard: %Flash Memory% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altufm_spi -- ============================================================ -- File Name: ufm_pack.vhd -- Megafunction Name(s): -- altufm_spi -- -- Simulation Library Files(s): -- altera;altera_mf;lpm;maxii -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 8.0 Build 231 07/10/2008 SP 1 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2008 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. --altufm_spi ACCESS_MODE="READ_WRITE" CBX_AUTO_BLACKBOX="ALL" CONFIG_MODE="EXTENDED" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 OSC_FREQUENCY=180000 PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 ncs sck si so --VERSION_BEGIN 8.0SP1 cbx_a_gray2bin 2008:06:02:292401 cbx_a_graycounter 2008:06:02:292401 cbx_altufm 2008:06:02:292401 cbx_cycloneii 2008:06:02:292401 cbx_flex10ke 2008:06:02:292401 cbx_lpm_add_sub 2008:06:02:292401 cbx_lpm_compare 2008:06:02:292401 cbx_lpm_counter 2008:06:02:292401 cbx_lpm_decode 2008:06:02:292401 cbx_lpm_mux 2008:06:02:292401 cbx_maxii 2008:06:02:292401 cbx_mgl 2008:06:02:292401 cbx_stratix 2008:06:02:292401 cbx_stratixii 2008:06:02:292401 cbx_util_mgl 2008:06:02:292401 VERSION_END LIBRARY altera_mf; USE altera_mf.all; LIBRARY lpm; USE lpm.all; LIBRARY maxii; USE maxii.all; --synthesis_resources = a_graycounter 4 lpm_counter 3 lut 111 maxii_ufm 1 TRI 1 LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY ufm_pack_altufm_spi_6ph IS PORT ( ncs : IN STD_LOGIC; sck : IN STD_LOGIC; si : IN STD_LOGIC; so : OUT STD_LOGIC ); END ufm_pack_altufm_spi_6ph; ARCHITECTURE RTL OF ufm_pack_altufm_spi_6ph IS ATTRIBUTE synthesis_clearbox : boolean; ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true; ATTRIBUTE ALTERA_ATTRIBUTE : string; ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "suppress_da_rule_internal=c101;suppress_da_rule_internal=c103;suppress_da_rule_internal=c104;suppress_da_rule_internal=c106;suppress_da_rule_internal=d101;suppress_da_rule_internal=r101;suppress_da_rule_internal=s102;suppress_da_rule_internal=s104"; SIGNAL wire_ce_add_cntr_w_lg_w_q_range161w164w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_ce_add_cntr_w_lg_w_q_range160w163w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_ce_add_cntr_aclr : STD_LOGIC; SIGNAL wire_w_lg_w_lg_ce_complete157w158w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_ce_add_cntr_clk_en : STD_LOGIC; SIGNAL wire_w_lg_w_lg_start_ce_inv155w156w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_ce_add_cntr_q : STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL wire_ce_add_cntr_w_q_range161w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_ce_add_cntr_w_q_range160w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_sec_cntr_w_lg_w_q_range169w188w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_sec_cntr_w_lg_w_q_range168w193w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_sec_cntr_clk_en : STD_LOGIC; SIGNAL wire_w_lg_ce_op_state167w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_sec_cntr_q : STD_LOGIC_VECTOR (1 DOWNTO 0); SIGNAL wire_sec_cntr_w_q_range168w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_sec_cntr_w_q_range169w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_stat_reg_cnt_clk_en : STD_LOGIC; SIGNAL wire_w_lg_w_lg_w_lg_ncs_wire2w251w276w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_stat_reg_cnt_q : STD_LOGIC_VECTOR (2 DOWNTO 0); SIGNAL wire_wrsr_cntr_clk_en : STD_LOGIC; SIGNAL wire_w_lg_w_lg_w_lg_ncs_wire2w251w252w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_wrsr_cntr_q : STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL addr_stdly_reg : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL dffe10 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL dffe12 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL dffe13 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL dffe16 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL dffe17 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL dffe18 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL dffe19 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL dffe2 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL dffe20 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL wire_dffe20_clrn : STD_LOGIC; SIGNAL wire_dffe20_ena : STD_LOGIC; SIGNAL dffe21 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL wire_dffe21_ena : STD_LOGIC; SIGNAL dffe22 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL dffe23 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL dffe24 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL dffe25 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL dffe26 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL dffe27 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL wire_dffe27_clrn : STD_LOGIC; SIGNAL dffe28 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL dffe29 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL wire_dffe29_ena : STD_LOGIC; SIGNAL dffe30 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL wire_dffe30_ena : STD_LOGIC; SIGNAL dffe31 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL dffe32 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL wire_dffe32_clrn : STD_LOGIC; SIGNAL dffe33 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL dffe34 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL dffe35 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL wire_dffe35_ena : STD_LOGIC; SIGNAL dffe36a : STD_LOGIC_VECTOR(1 DOWNTO 0) -- synopsys translate_off := (OTHERS => '0') -- synopsys translate_on ; SIGNAL wire_dffe37a_d : STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL dffe37a : STD_LOGIC_VECTOR(3 DOWNTO 0) -- synopsys translate_off := (OTHERS => '0') -- synopsys translate_on ; SIGNAL wire_dffe37a_ena : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL dffe38 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL dffe39 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL dffe4 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL wire_dffe40a_d : STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL dffe40a : STD_LOGIC_VECTOR(7 DOWNTO 0) -- synopsys translate_off := (OTHERS => '0') -- synopsys translate_on ; SIGNAL wire_dffe40a_ena : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL wire_dffe40a_w_lg_w_lg_w_q_range287w338w339w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_dffe40a_w_lg_w_q_range292w294w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_dffe40a_w_lg_w_q_range297w299w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_dffe40a_w_lg_w_q_range302w304w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_dffe40a_w_lg_w_q_range307w309w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_dffe40a_w_lg_w_q_range310w312w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_dffe40a_w_lg_w_q_range313w315w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_dffe40a_w_lg_w_q_range316w322w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_dffe40a_w_lg_w_q_range287w290w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_dffe40a_w_lg_w_q_range287w338w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_dffe40a_w_lg_w_lg_w_q_range316w322w323w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_dffe40a_w_q_range292w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_dffe40a_w_q_range297w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_dffe40a_w_q_range302w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_dffe40a_w_q_range307w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_dffe40a_w_q_range310w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_dffe40a_w_q_range313w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_dffe40a_w_q_range316w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_dffe40a_w_q_range287w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL dffe41 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL wire_dffe41_ena : STD_LOGIC; SIGNAL dffe42 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL wire_dffe42_ena : STD_LOGIC; SIGNAL wire_dffe5a_d : STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL dffe5a : STD_LOGIC_VECTOR(7 DOWNTO 0) -- synopsys translate_off := (OTHERS => '0') -- synopsys translate_on ; SIGNAL wire_dffe5a_ena : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL dffe6 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL wire_dffe7a_d : STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL dffe7a : STD_LOGIC_VECTOR(7 DOWNTO 0) -- synopsys translate_off := (OTHERS => '0') -- synopsys translate_on ; SIGNAL wire_dffe7a_ena : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL dffe8 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL dffe9 : STD_LOGIC -- synopsys translate_off := '0' -- synopsys translate_on ; SIGNAL wire_cntr11_clk_en : STD_LOGIC; SIGNAL wire_w_lg_w_lg_w_lg_ncs_wire2w80w81w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_cntr11_q : STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL wire_cntr14_w_lg_w_q_range92w199w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_cntr14_clk_en : STD_LOGIC; SIGNAL wire_w_lg_w_lg_ncs_wire2w213w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_cntr14_q : STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL wire_cntr14_w_q_range92w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_cntr3_w_lg_w_q_range8w274w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_cntr3_w_lg_w_q_range7w273w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_cntr3_clk_en : STD_LOGIC; SIGNAL wire_w_lg_w_lg_w_lg_ncs_wire2w5w6w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_cntr3_clock : STD_LOGIC; SIGNAL wire_cntr3_q : STD_LOGIC_VECTOR (2 DOWNTO 0); SIGNAL wire_cntr3_w_q_range8w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_cntr3_w_q_range7w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_maxii_ufm_block1_bgpbusy : STD_LOGIC; SIGNAL wire_maxii_ufm_block1_busy : STD_LOGIC; SIGNAL wire_maxii_ufm_block1_drdout : STD_LOGIC; SIGNAL wire_maxii_ufm_block1_osc : STD_LOGIC; SIGNAL wire_tri_buf15_out : STD_LOGIC; SIGNAL wire_tri_buf15_oe : STD_LOGIC; SIGNAL wire_tri_buf15_in : STD_LOGIC; SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sck_wire215w216w217w218w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_w_lg_w_lg_ce_pdcmplt_dly189w190w191w192w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_w_lg_w_lg_ncs_wire2w14w15w16w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_w_lg_w_lg_sck_wire1w219w220w221w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_w_lg_sck_wire215w216w217w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_w_lg_start_ce194w195w196w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_w_lg_ce_pdcmplt_dly189w190w191w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_w_lg_ncs_wire2w14w15w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_w_lg_ncs_wire2w262w263w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_w_lg_sck_wire1w219w220w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_bp0_state332w333w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_ce_pad_complete175w176w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_sck_wire215w216w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_se_op233w234w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_start_ce194w195w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_ufm_drdout340w341w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_write_op209w210w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_write_op228w229w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_ce_pdcmplt_dly189w190w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_ncs_wire2w286w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_ncs_wire2w251w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_ncs_wire2w14w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_ncs_wire2w262w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_sck_wire1w219w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_w_lg_ufm_busy318w319w320w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_addr_stdly343w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_bp0_state332w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_bp0_state300w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_bp1_state305w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_ce_op_state171w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_ce_pad_complete175w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_op_complete182w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_op_complete_dly284w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_sck_wire215w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_se_op233w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_si_wire184w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_start_ce194w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_start_ce_inv155w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_ufm_drdout340w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_ufm_osc198w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_wen_state295w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_write_op209w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_write_op228w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_addr_complete79w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_addr_complete_state200w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_addr_state214w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_bp0bp1_protect150w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_ce_pad_complete154w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_ce_pdcmplt_dly189w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_ce_pdcmplt_inv187w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_data_complete208w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_erase_complete236w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_ncs_wire2w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_op_code6289w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_op_complete3w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_op_complete_state13w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_prog_complete231w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_sck_wire1w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_sec2_complete153w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_streg_complete321w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_ufm_bgpbusy12w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_ufm_busy75w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_wrdi_op239w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_wrsr_complete250w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_w_lg_w_lg_start_ce194w195w196w197w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_bp0_state300w301w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_bp1_state305w306w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_op_complete_dly284w285w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_wen_state295w296w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_ufm_busy318w319w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_w_lg_write_op180w181w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_data_state344w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_ufm_busy318w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL wire_w_lg_write_op180w : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL addr_bit7 : STD_LOGIC; SIGNAL addr_bit8 : STD_LOGIC; SIGNAL addr_complete : STD_LOGIC; SIGNAL addr_complete_state : STD_LOGIC; SIGNAL addr_state : STD_LOGIC; SIGNAL addr_stdly : STD_LOGIC; SIGNAL bp0_state : STD_LOGIC; SIGNAL bp0bp1_protect : STD_LOGIC; SIGNAL bp1_state : STD_LOGIC; SIGNAL busy_dly : STD_LOGIC; SIGNAL ce_complete : STD_LOGIC; SIGNAL ce_op : STD_LOGIC; SIGNAL ce_op_state : STD_LOGIC; SIGNAL ce_pad_complete : STD_LOGIC; SIGNAL ce_pdcmplt_dly : STD_LOGIC; SIGNAL ce_pdcmplt_inv : STD_LOGIC; SIGNAL ce_state : STD_LOGIC; SIGNAL chip_erase_add : STD_LOGIC; SIGNAL circuit_reset : STD_LOGIC; SIGNAL data_complete : STD_LOGIC; SIGNAL data_state : STD_LOGIC; SIGNAL erase_complete : STD_LOGIC; SIGNAL erase_state : STD_LOGIC; SIGNAL ncs_wire : STD_LOGIC; SIGNAL op_code6 : STD_LOGIC; SIGNAL op_complete : STD_LOGIC; SIGNAL op_complete_dly : STD_LOGIC; SIGNAL op_complete_state : STD_LOGIC; SIGNAL op_state : STD_LOGIC; SIGNAL prog_complete : STD_LOGIC; SIGNAL prog_state : STD_LOGIC; SIGNAL rdsr_op : STD_LOGIC; SIGNAL read_op : STD_LOGIC; SIGNAL read_op_state : STD_LOGIC; SIGNAL sck_wire : STD_LOGIC; SIGNAL se_op : STD_LOGIC; SIGNAL se_op_state : STD_LOGIC; SIGNAL sec2_complete : STD_LOGIC; SIGNAL si_wire : STD_LOGIC; SIGNAL so_wire : STD_LOGIC; SIGNAL start_ce : STD_LOGIC; SIGNAL start_ce_inv : STD_LOGIC; SIGNAL streg_complete : STD_LOGIC; SIGNAL ufm_arclk : STD_LOGIC; SIGNAL ufm_ardin : STD_LOGIC; SIGNAL ufm_arshft : STD_LOGIC; SIGNAL ufm_bgpbusy : STD_LOGIC; SIGNAL ufm_busy : STD_LOGIC; SIGNAL ufm_drclk : STD_LOGIC; SIGNAL ufm_drdin : STD_LOGIC; SIGNAL ufm_drdout : STD_LOGIC; SIGNAL ufm_drshft : STD_LOGIC; SIGNAL ufm_erase : STD_LOGIC; SIGNAL ufm_osc : STD_LOGIC; SIGNAL ufm_oscena : STD_LOGIC; SIGNAL ufm_program : STD_LOGIC; SIGNAL wen_state : STD_LOGIC; SIGNAL wrdi_op : STD_LOGIC; SIGNAL wren_op : STD_LOGIC; SIGNAL write_op : STD_LOGIC; SIGNAL write_op_state : STD_LOGIC; SIGNAL wrsr_complete : STD_LOGIC; SIGNAL wrsr_op : STD_LOGIC; COMPONENT a_graycounter GENERIC ( PVALUE : NATURAL := 0; WIDTH : NATURAL; lpm_type : STRING := "a_graycounter" ); PORT ( aclr : IN STD_LOGIC := '0'; clk_en : IN STD_LOGIC := '1'; clock : IN STD_LOGIC; cnt_en : IN STD_LOGIC := '1'; q : OUT STD_LOGIC_VECTOR(width-1 DOWNTO 0); qbin : OUT STD_LOGIC_VECTOR(width-1 DOWNTO 0); sclr : IN STD_LOGIC := '0'; updown : IN STD_LOGIC := '1' ); END COMPONENT; COMPONENT lpm_counter GENERIC ( lpm_avalue : STRING := "0"; lpm_direction : STRING := "DEFAULT"; lpm_modulus : NATURAL := 0; lpm_port_updown : STRING := "PORT_CONNECTIVITY"; lpm_pvalue : STRING := "0"; lpm_svalue : STRING := "0"; lpm_width : NATURAL; lpm_type : STRING := "lpm_counter" ); PORT ( aclr : IN STD_LOGIC := '0'; aload : IN STD_LOGIC := '0'; aset : IN STD_LOGIC := '0'; cin : IN STD_LOGIC := '1'; clk_en : IN STD_LOGIC := '1'; clock : IN STD_LOGIC; cnt_en : IN STD_LOGIC := '1'; cout : OUT STD_LOGIC; data : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); eq : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); q : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0); sclr : IN STD_LOGIC := '0'; sload : IN STD_LOGIC := '0'; sset : IN STD_LOGIC := '0'; updown : IN STD_LOGIC := '1' ); END COMPONENT; COMPONENT maxii_ufm GENERIC ( ADDRESS_WIDTH : NATURAL := 9; ERASE_TIME : NATURAL := 500000000; INIT_FILE : STRING := "UNUSED"; mem1 : STD_LOGIC_VECTOR(511 DOWNTO 0) := "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111"; mem10 : STD_LOGIC_VECTOR(511 DOWNTO 0) := "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111"; mem11 : STD_LOGIC_VECTOR(511 DOWNTO 0) := "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111"; mem12 : STD_LOGIC_VECTOR(511 DOWNTO 0) := "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111"; mem13 : STD_LOGIC_VECTOR(511 DOWNTO 0) := "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111"; mem14 : STD_LOGIC_VECTOR(511 DOWNTO 0) := "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111"; mem15 : STD_LOGIC_VECTOR(511 DOWNTO 0) := "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111"; mem16 : STD_LOGIC_VECTOR(511 DOWNTO 0) := "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111"; mem2 : STD_LOGIC_VECTOR(511 DOWNTO 0) := "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111"; mem3 : STD_LOGIC_VECTOR(511 DOWNTO 0) := "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111"; mem4 : STD_LOGIC_VECTOR(511 DOWNTO 0) := "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111"; mem5 : STD_LOGIC_VECTOR(511 DOWNTO 0) := "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111"; mem6 : STD_LOGIC_VECTOR(511 DOWNTO 0) := "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111"; mem7 : STD_LOGIC_VECTOR(511 DOWNTO 0) := "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111"; mem8 : STD_LOGIC_VECTOR(511 DOWNTO 0) := "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111"; mem9 : STD_LOGIC_VECTOR(511 DOWNTO 0) := "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111"; OSC_SIM_SETTING : NATURAL := 180000; PROGRAM_TIME : NATURAL := 1600000; lpm_type : STRING := "maxii_ufm" ); PORT ( arclk : IN STD_LOGIC := '0'; ardin : IN STD_LOGIC := '0'; arshft : IN STD_LOGIC := '1'; bgpbusy : OUT STD_LOGIC; busy : OUT STD_LOGIC; drclk : IN STD_LOGIC := '0'; drdin : IN STD_LOGIC := '0'; drdout : OUT STD_LOGIC; drshft : IN STD_LOGIC := '1'; erase : IN STD_LOGIC := '0'; osc : OUT STD_LOGIC; oscena : IN STD_LOGIC := '0'; program : IN STD_LOGIC := '0' ); END COMPONENT; BEGIN wire_w_lg_w_lg_w_lg_w_lg_sck_wire215w216w217w218w(0) <= wire_w_lg_w_lg_w_lg_sck_wire215w216w217w(0) AND write_op_state; wire_w_lg_w_lg_w_lg_w_lg_ce_pdcmplt_dly189w190w191w192w(0) <= wire_w_lg_w_lg_w_lg_ce_pdcmplt_dly189w190w191w(0) AND wire_w_lg_ce_pdcmplt_inv187w(0); wire_w_lg_w_lg_w_lg_w_lg_ncs_wire2w14w15w16w(0) <= wire_w_lg_w_lg_w_lg_ncs_wire2w14w15w(0) AND wire_w_lg_ufm_bgpbusy12w(0); wire_w_lg_w_lg_w_lg_w_lg_sck_wire1w219w220w221w(0) <= wire_w_lg_w_lg_w_lg_sck_wire1w219w220w(0) AND read_op_state; wire_w_lg_w_lg_w_lg_sck_wire215w216w217w(0) <= wire_w_lg_w_lg_sck_wire215w216w(0) AND write_op; wire_w_lg_w_lg_w_lg_start_ce194w195w196w(0) <= wire_w_lg_w_lg_start_ce194w195w(0) AND wire_sec_cntr_w_lg_w_q_range169w188w(0); wire_w_lg_w_lg_w_lg_ce_pdcmplt_dly189w190w191w(0) <= wire_w_lg_w_lg_ce_pdcmplt_dly189w190w(0) AND wire_sec_cntr_w_lg_w_q_range169w188w(0); wire_w_lg_w_lg_w_lg_ncs_wire2w14w15w(0) <= wire_w_lg_w_lg_ncs_wire2w14w(0) AND wire_w_lg_op_complete_state13w(0); wire_w_lg_w_lg_w_lg_ncs_wire2w262w263w(0) <= wire_w_lg_w_lg_ncs_wire2w262w(0) AND wire_w_lg_wrsr_complete250w(0); wire_w_lg_w_lg_w_lg_sck_wire1w219w220w(0) <= wire_w_lg_w_lg_sck_wire1w219w(0) AND read_op; wire_w_lg_w_lg_bp0_state332w333w(0) <= wire_w_lg_bp0_state332w(0) AND addr_bit7; wire_w_lg_w_lg_ce_pad_complete175w176w(0) <= wire_w_lg_ce_pad_complete175w(0) AND wen_state; wire_w_lg_w_lg_sck_wire215w216w(0) <= wire_w_lg_sck_wire215w(0) AND wire_w_lg_addr_state214w(0); wire_w_lg_w_lg_se_op233w234w(0) <= wire_w_lg_se_op233w(0) AND wen_state; wire_w_lg_w_lg_start_ce194w195w(0) <= wire_w_lg_start_ce194w(0) AND wire_sec_cntr_w_lg_w_q_range168w193w(0); wire_w_lg_w_lg_ufm_drdout340w341w(0) <= wire_w_lg_ufm_drdout340w(0) AND read_op_state; wire_w_lg_w_lg_write_op209w210w(0) <= wire_w_lg_write_op209w(0) AND data_state; wire_w_lg_w_lg_write_op228w229w(0) <= wire_w_lg_write_op228w(0) AND wen_state; wire_w_lg_w_lg_ce_pdcmplt_dly189w190w(0) <= wire_w_lg_ce_pdcmplt_dly189w(0) AND wire_sec_cntr_w_q_range168w(0); wire_w_lg_w_lg_ncs_wire2w286w(0) <= wire_w_lg_ncs_wire2w(0) AND wire_w_lg_w_lg_op_complete_dly284w285w(0); wire_w_lg_w_lg_ncs_wire2w251w(0) <= wire_w_lg_ncs_wire2w(0) AND op_complete; wire_w_lg_w_lg_ncs_wire2w14w(0) <= wire_w_lg_ncs_wire2w(0) AND op_state; wire_w_lg_w_lg_ncs_wire2w262w(0) <= wire_w_lg_ncs_wire2w(0) AND wrsr_op; wire_w_lg_w_lg_sck_wire1w219w(0) <= wire_w_lg_sck_wire1w(0) AND addr_complete; wire_w_lg_w_lg_w_lg_ufm_busy318w319w320w(0) <= wire_w_lg_w_lg_ufm_busy318w319w(0) AND streg_complete; wire_w_lg_addr_stdly343w(0) <= addr_stdly AND addr_complete_state; wire_w_lg_bp0_state332w(0) <= bp0_state AND addr_bit8; wire_w_lg_bp0_state300w(0) <= bp0_state AND op_code6; wire_w_lg_bp1_state305w(0) <= bp1_state AND op_code6; wire_w_lg_ce_op_state171w(0) <= ce_op_state AND wire_w_lg_ce_pad_complete154w(0); wire_w_lg_ce_pad_complete175w(0) <= ce_pad_complete AND ce_op_state; wire_w_lg_op_complete182w(0) <= op_complete AND wire_w_lg_w_lg_write_op180w181w(0); wire_w_lg_op_complete_dly284w(0) <= op_complete_dly AND rdsr_op; wire_w_lg_sck_wire215w(0) <= sck_wire AND addr_complete; wire_w_lg_se_op233w(0) <= se_op AND se_op_state; wire_w_lg_si_wire184w(0) <= si_wire AND wire_w_lg_w_lg_write_op180w181w(0); wire_w_lg_start_ce194w(0) <= start_ce AND wire_w_lg_ce_pdcmplt_inv187w(0); wire_w_lg_start_ce_inv155w(0) <= start_ce_inv AND wire_w_lg_ce_pad_complete154w(0); wire_w_lg_ufm_drdout340w(0) <= ufm_drdout AND read_op; wire_w_lg_ufm_osc198w(0) <= ufm_osc AND wire_w_lg_w_lg_w_lg_w_lg_start_ce194w195w196w197w(0); wire_w_lg_wen_state295w(0) <= wen_state AND op_code6; wire_w_lg_write_op209w(0) <= write_op AND wire_w_lg_data_complete208w(0); wire_w_lg_write_op228w(0) <= write_op AND write_op_state; wire_w_lg_addr_complete79w(0) <= NOT addr_complete; wire_w_lg_addr_complete_state200w(0) <= NOT addr_complete_state; wire_w_lg_addr_state214w(0) <= NOT addr_state; wire_w_lg_bp0bp1_protect150w(0) <= NOT bp0bp1_protect; wire_w_lg_ce_pad_complete154w(0) <= NOT ce_pad_complete; wire_w_lg_ce_pdcmplt_dly189w(0) <= NOT ce_pdcmplt_dly; wire_w_lg_ce_pdcmplt_inv187w(0) <= NOT ce_pdcmplt_inv; wire_w_lg_data_complete208w(0) <= NOT data_complete; wire_w_lg_erase_complete236w(0) <= NOT erase_complete; wire_w_lg_ncs_wire2w(0) <= NOT ncs_wire; wire_w_lg_op_code6289w(0) <= NOT op_code6; wire_w_lg_op_complete3w(0) <= NOT op_complete; wire_w_lg_op_complete_state13w(0) <= NOT op_complete_state; wire_w_lg_prog_complete231w(0) <= NOT prog_complete; wire_w_lg_sck_wire1w(0) <= NOT sck_wire; wire_w_lg_sec2_complete153w(0) <= NOT sec2_complete; wire_w_lg_streg_complete321w(0) <= NOT streg_complete; wire_w_lg_ufm_bgpbusy12w(0) <= NOT ufm_bgpbusy; wire_w_lg_ufm_busy75w(0) <= NOT ufm_busy; wire_w_lg_wrdi_op239w(0) <= NOT wrdi_op; wire_w_lg_wrsr_complete250w(0) <= NOT wrsr_complete; wire_w_lg_w_lg_w_lg_w_lg_start_ce194w195w196w197w(0) <= wire_w_lg_w_lg_w_lg_start_ce194w195w196w(0) OR wire_w_lg_w_lg_w_lg_w_lg_ce_pdcmplt_dly189w190w191w192w(0); wire_w_lg_w_lg_bp0_state300w301w(0) <= wire_w_lg_bp0_state300w(0) OR wire_dffe40a_w_lg_w_q_range297w299w(0); wire_w_lg_w_lg_bp1_state305w306w(0) <= wire_w_lg_bp1_state305w(0) OR wire_dffe40a_w_lg_w_q_range302w304w(0); wire_w_lg_w_lg_op_complete_dly284w285w(0) <= wire_w_lg_op_complete_dly284w(0) OR op_code6; wire_w_lg_w_lg_wen_state295w296w(0) <= wire_w_lg_wen_state295w(0) OR wire_dffe40a_w_lg_w_q_range292w294w(0); wire_w_lg_w_lg_ufm_busy318w319w(0) <= wire_w_lg_ufm_busy318w(0) OR ufm_bgpbusy; wire_w_lg_w_lg_write_op180w181w(0) <= wire_w_lg_write_op180w(0) OR se_op; wire_w_lg_data_state344w(0) <= data_state OR wire_w_lg_addr_stdly343w(0); wire_w_lg_ufm_busy318w(0) <= ufm_busy OR ce_op_state; wire_w_lg_write_op180w(0) <= write_op OR read_op; addr_bit7 <= dffe42; addr_bit8 <= dffe41; addr_complete <= (((wire_cntr11_q(0) AND wire_cntr11_q(1)) AND wire_cntr11_q(2)) AND wire_cntr11_q(3)); addr_complete_state <= dffe12; addr_state <= dffe10; addr_stdly <= addr_stdly_reg; bp0_state <= dffe36a(0); bp0bp1_protect <= (((bp0_state AND bp1_state) OR (bp1_state AND addr_bit8)) OR wire_w_lg_w_lg_bp0_state332w333w(0)); bp1_state <= dffe36a(1); busy_dly <= dffe31; ce_complete <= dffe28; ce_op <= ((((((((NOT dffe5a(7)) AND dffe5a(6)) AND dffe5a(5)) AND (NOT dffe5a(4))) AND (NOT dffe5a(3))) AND (NOT dffe5a(2))) AND (NOT dffe5a(1))) AND (NOT dffe5a(0))); ce_op_state <= dffe20; ce_pad_complete <= ((wire_ce_add_cntr_w_lg_w_q_range161w164w(0) AND wire_ce_add_cntr_q(2)) AND wire_ce_add_cntr_q(3)); ce_pdcmplt_dly <= dffe25; ce_pdcmplt_inv <= dffe24; ce_state <= dffe29; chip_erase_add <= dffe26; circuit_reset <= dffe17; data_complete <= (((wire_cntr14_q(0) AND wire_cntr14_q(1)) AND wire_cntr14_q(2)) AND wire_cntr14_q(3)); data_state <= dffe13; erase_complete <= dffe32; erase_state <= dffe34; ncs_wire <= ncs; op_code6 <= dffe39; op_complete <= ((wire_cntr3_q(0) AND wire_cntr3_q(1)) AND wire_cntr3_q(2)); op_complete_dly <= dffe38; op_complete_state <= dffe4; op_state <= dffe2; prog_complete <= dffe32; prog_state <= dffe33; rdsr_op <= (((((((((NOT dffe7a(7)) AND (NOT dffe7a(6))) AND (NOT dffe7a(5))) AND (NOT dffe7a(4))) AND (NOT dffe7a(3))) AND dffe7a(2)) AND (NOT dffe7a(1))) AND dffe7a(0)) AND op_complete); read_op <= ((((((((NOT dffe5a(7)) AND (NOT dffe5a(6))) AND (NOT dffe5a(5))) AND (NOT dffe5a(4))) AND (NOT dffe5a(3))) AND (NOT dffe5a(2))) AND dffe5a(1)) AND dffe5a(0)); read_op_state <= dffe9; sck_wire <= sck; se_op <= ((((((((NOT dffe5a(7)) AND (NOT dffe5a(6))) AND dffe5a(5)) AND (NOT dffe5a(4))) AND (NOT dffe5a(3))) AND (NOT dffe5a(2))) AND (NOT dffe5a(1))) AND (NOT dffe5a(0))); se_op_state <= dffe19; sec2_complete <= (wire_sec_cntr_q(0) AND wire_sec_cntr_q(1)); si_wire <= si; so <= so_wire; so_wire <= wire_tri_buf15_out; start_ce <= dffe23; start_ce_inv <= dffe22; streg_complete <= (((NOT wire_stat_reg_cnt_q(0)) AND (NOT wire_stat_reg_cnt_q(1))) AND wire_stat_reg_cnt_q(2)); ufm_arclk <= ((((sck_wire AND addr_state) AND wire_w_lg_addr_complete_state200w(0)) OR wire_cntr14_w_lg_w_q_range92w199w(0)) OR wire_w_lg_ufm_osc198w(0)); ufm_ardin <= ((wire_w_lg_si_wire184w(0) AND wire_w_lg_ufm_bgpbusy12w(0)) OR chip_erase_add); ufm_arshft <= ((wire_w_lg_op_complete182w(0) AND wire_w_lg_addr_complete_state200w(0)) OR start_ce_inv); ufm_bgpbusy <= wire_maxii_ufm_block1_bgpbusy; ufm_busy <= wire_maxii_ufm_block1_busy; ufm_drclk <= (wire_w_lg_w_lg_w_lg_w_lg_sck_wire1w219w220w221w(0) OR wire_w_lg_w_lg_w_lg_w_lg_sck_wire215w216w217w218w(0)); ufm_drdin <= (si_wire AND write_op_state); ufm_drdout <= wire_maxii_ufm_block1_drdout; ufm_drshft <= (NOT (((addr_state AND addr_complete) OR data_complete) AND read_op_state)); ufm_erase <= ((erase_state AND wire_w_lg_erase_complete236w(0)) OR ce_state); ufm_osc <= wire_maxii_ufm_block1_osc; ufm_oscena <= '1'; ufm_program <= (prog_state AND wire_w_lg_prog_complete231w(0)); wen_state <= dffe35; wrdi_op <= ((((((((NOT dffe7a(7)) AND (NOT dffe7a(6))) AND (NOT dffe7a(5))) AND (NOT dffe7a(4))) AND (NOT dffe7a(3))) AND dffe7a(2)) AND (NOT dffe7a(1))) AND (NOT dffe7a(0))); wren_op <= ((((((((NOT dffe7a(7)) AND (NOT dffe7a(6))) AND (NOT dffe7a(5))) AND (NOT dffe7a(4))) AND (NOT dffe7a(3))) AND dffe7a(2)) AND dffe7a(1)) AND (NOT dffe7a(0))); write_op <= ((((((((NOT dffe5a(7)) AND (NOT dffe5a(6))) AND (NOT dffe5a(5))) AND (NOT dffe5a(4))) AND (NOT dffe5a(3))) AND (NOT dffe5a(2))) AND dffe5a(1)) AND (NOT dffe5a(0))); write_op_state <= dffe18; wrsr_complete <= ((((NOT wire_wrsr_cntr_q(0)) AND (NOT wire_wrsr_cntr_q(1))) AND wire_wrsr_cntr_q(2)) AND wire_wrsr_cntr_q(3)); wrsr_op <= (((((((((NOT dffe7a(7)) AND (NOT dffe7a(6))) AND (NOT dffe7a(5))) AND (NOT dffe7a(4))) AND (NOT dffe7a(3))) AND (NOT dffe7a(2))) AND (NOT dffe7a(1))) AND dffe7a(0)) AND op_complete); wire_ce_add_cntr_w_lg_w_q_range161w164w(0) <= wire_ce_add_cntr_w_q_range161w(0) AND wire_ce_add_cntr_w_lg_w_q_range160w163w(0); wire_ce_add_cntr_w_lg_w_q_range160w163w(0) <= NOT wire_ce_add_cntr_w_q_range160w(0); wire_ce_add_cntr_aclr <= wire_w_lg_w_lg_ce_complete157w158w(0); wire_w_lg_w_lg_ce_complete157w158w(0) <= (ce_complete AND wire_w_lg_ufm_bgpbusy12w(0)) OR op_state; wire_ce_add_cntr_clk_en <= wire_w_lg_w_lg_start_ce_inv155w156w(0); wire_w_lg_w_lg_start_ce_inv155w156w(0) <= wire_w_lg_start_ce_inv155w(0) AND wire_w_lg_sec2_complete153w(0); wire_ce_add_cntr_w_q_range161w(0) <= wire_ce_add_cntr_q(0); wire_ce_add_cntr_w_q_range160w(0) <= wire_ce_add_cntr_q(1); ce_add_cntr : a_graycounter GENERIC MAP ( WIDTH => 4 ) PORT MAP ( aclr => wire_ce_add_cntr_aclr, clk_en => wire_ce_add_cntr_clk_en, clock => ufm_osc, q => wire_ce_add_cntr_q ); wire_sec_cntr_w_lg_w_q_range169w188w(0) <= NOT wire_sec_cntr_w_q_range169w(0); wire_sec_cntr_w_lg_w_q_range168w193w(0) <= NOT wire_sec_cntr_w_q_range168w(0); wire_sec_cntr_clk_en <= wire_w_lg_ce_op_state167w(0); wire_w_lg_ce_op_state167w(0) <= ce_op_state AND wire_w_lg_sec2_complete153w(0); wire_sec_cntr_w_q_range168w(0) <= wire_sec_cntr_q(0); wire_sec_cntr_w_q_range169w(0) <= wire_sec_cntr_q(1); sec_cntr : a_graycounter GENERIC MAP ( WIDTH => 2 ) PORT MAP ( aclr => op_state, clk_en => wire_sec_cntr_clk_en, clock => ce_complete, q => wire_sec_cntr_q ); wire_stat_reg_cnt_clk_en <= wire_w_lg_w_lg_w_lg_ncs_wire2w251w276w(0); wire_w_lg_w_lg_w_lg_ncs_wire2w251w276w(0) <= wire_w_lg_w_lg_ncs_wire2w251w(0) AND rdsr_op; stat_reg_cnt : a_graycounter GENERIC MAP ( WIDTH => 3 ) PORT MAP ( aclr => circuit_reset, clk_en => wire_stat_reg_cnt_clk_en, clock => sck_wire, q => wire_stat_reg_cnt_q ); wire_wrsr_cntr_clk_en <= wire_w_lg_w_lg_w_lg_ncs_wire2w251w252w(0); wire_w_lg_w_lg_w_lg_ncs_wire2w251w252w(0) <= wire_w_lg_w_lg_ncs_wire2w251w(0) AND wire_w_lg_wrsr_complete250w(0); wrsr_cntr : a_graycounter GENERIC MAP ( WIDTH => 4 ) PORT MAP ( aclr => circuit_reset, clk_en => wire_wrsr_cntr_clk_en, clock => sck_wire, q => wire_wrsr_cntr_q ); PROCESS (sck_wire) BEGIN IF (sck_wire = '0' AND sck_wire'event) THEN addr_stdly_reg <= addr_state; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe10 <= '0'; ELSIF (sck_wire = '1' AND sck_wire'event) THEN IF (ncs_wire = '0') THEN dffe10 <= (wire_w_lg_op_complete182w(0) AND wire_w_lg_addr_complete79w(0)); END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe12 <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (ncs_wire = '0') THEN dffe12 <= addr_complete; END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe13 <= '0'; ELSIF (sck_wire = '1' AND sck_wire'event) THEN IF (ncs_wire = '0') THEN dffe13 <= (addr_complete AND wire_w_lg_write_op180w(0)); END IF; END IF; END PROCESS; PROCESS (ufm_osc) BEGIN IF (ufm_osc = '1' AND ufm_osc'event) THEN dffe16 <= ncs_wire; END IF; END PROCESS; PROCESS (ufm_osc) BEGIN IF (ufm_osc = '1' AND ufm_osc'event) THEN dffe17 <= dffe16; END IF; END PROCESS; PROCESS (sck_wire) BEGIN IF (sck_wire = '1' AND sck_wire'event) THEN IF (ncs_wire = '0') THEN dffe18 <= (((op_complete_state AND write_op) AND wire_w_lg_ufm_busy75w(0)) AND wire_w_lg_ufm_bgpbusy12w(0)); END IF; END IF; END PROCESS; PROCESS (sck_wire) BEGIN IF (sck_wire = '1' AND sck_wire'event) THEN IF (ncs_wire = '0') THEN dffe19 <= (((op_complete_state AND se_op) AND wire_w_lg_ufm_busy75w(0)) AND wire_w_lg_ufm_bgpbusy12w(0)); END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe2 <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (ncs_wire = '0') THEN dffe2 <= wire_w_lg_op_complete3w(0); END IF; END IF; END PROCESS; PROCESS (ncs_wire, wire_dffe20_clrn) BEGIN IF (wire_dffe20_clrn = '0') THEN dffe20 <= '0'; ELSIF (ncs_wire = '1' AND ncs_wire'event) THEN IF (wire_dffe20_ena = '1') THEN dffe20 <= (op_complete AND ce_op); END IF; END IF; END PROCESS; wire_dffe20_clrn <= (NOT (sec2_complete OR ufm_bgpbusy)); wire_dffe20_ena <= (wire_w_lg_ufm_busy75w(0) AND wire_w_lg_ufm_bgpbusy12w(0)); PROCESS (ufm_osc) BEGIN IF (ufm_osc = '1' AND ufm_osc'event) THEN IF (wire_dffe21_ena = '1') THEN dffe21 <= ce_op_state; END IF; END IF; END PROCESS; wire_dffe21_ena <= (wen_state AND wire_w_lg_bp0bp1_protect150w(0)); PROCESS (ufm_osc) BEGIN IF (ufm_osc = '0' AND ufm_osc'event) THEN dffe22 <= dffe21; END IF; END PROCESS; PROCESS (ufm_osc) BEGIN IF (ufm_osc = '1' AND ufm_osc'event) THEN dffe23 <= dffe21; END IF; END PROCESS; PROCESS (ufm_osc) BEGIN IF (ufm_osc = '0' AND ufm_osc'event) THEN dffe24 <= ce_pad_complete; END IF; END PROCESS; PROCESS (ufm_osc) BEGIN IF (ufm_osc = '1' AND ufm_osc'event) THEN dffe25 <= ce_pad_complete; END IF; END PROCESS; PROCESS (ufm_osc) BEGIN IF (ufm_osc = '0' AND ufm_osc'event) THEN dffe26 <= (wire_w_lg_ce_op_state171w(0) AND wire_sec_cntr_q(0)); END IF; END PROCESS; PROCESS (busy_dly, wire_dffe27_clrn) BEGIN IF (wire_dffe27_clrn = '0') THEN dffe27 <= '0'; ELSIF (busy_dly = '0' AND busy_dly'event) THEN dffe27 <= '1'; END IF; END PROCESS; wire_dffe27_clrn <= (ufm_erase AND wire_ce_add_cntr_q(3)); PROCESS (ufm_osc) BEGIN IF (ufm_osc = '1' AND ufm_osc'event) THEN dffe28 <= dffe27; END IF; END PROCESS; PROCESS (ufm_osc, ce_complete) BEGIN IF (ce_complete = '1') THEN dffe29 <= '0'; ELSIF (ufm_osc = '1' AND ufm_osc'event) THEN IF (wire_dffe29_ena = '1') THEN dffe29 <= '1'; END IF; END IF; END PROCESS; wire_dffe29_ena <= ((wire_w_lg_w_lg_ce_pad_complete175w176w(0) AND wire_w_lg_bp0bp1_protect150w(0)) AND wire_w_lg_ufm_bgpbusy12w(0)); PROCESS (ufm_osc, op_state) BEGIN IF (op_state = '1') THEN dffe30 <= '0'; ELSIF (ufm_osc = '1' AND ufm_osc'event) THEN IF (wire_dffe30_ena = '1') THEN dffe30 <= ufm_busy; END IF; END IF; END PROCESS; wire_dffe30_ena <= (ufm_program OR ufm_erase); PROCESS (ufm_osc, op_state) BEGIN IF (op_state = '1') THEN dffe31 <= '0'; ELSIF (ufm_osc = '0' AND ufm_osc'event) THEN dffe31 <= dffe30; END IF; END PROCESS; PROCESS (busy_dly, wire_dffe32_clrn) BEGIN IF (wire_dffe32_clrn = '0') THEN dffe32 <= '0'; ELSIF (busy_dly = '0' AND busy_dly'event) THEN dffe32 <= '1'; END IF; END PROCESS; wire_dffe32_clrn <= (NOT (op_state AND wire_w_lg_ufm_busy75w(0))); PROCESS (sck_wire, prog_complete) BEGIN IF (prog_complete = '1') THEN dffe33 <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (data_complete = '1') THEN dffe33 <= (wire_w_lg_w_lg_write_op228w229w(0) AND wire_w_lg_bp0bp1_protect150w(0)); END IF; END IF; END PROCESS; PROCESS (sck_wire, erase_complete) BEGIN IF (erase_complete = '1') THEN dffe34 <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (addr_complete = '1') THEN dffe34 <= (wire_w_lg_w_lg_se_op233w234w(0) AND wire_w_lg_bp0bp1_protect150w(0)); END IF; END IF; END PROCESS; PROCESS (ncs_wire) BEGIN IF (ncs_wire = '1' AND ncs_wire'event) THEN IF (wire_dffe35_ena = '1') THEN dffe35 <= (wren_op OR wire_w_lg_wrdi_op239w(0)); END IF; END IF; END PROCESS; wire_dffe35_ena <= (wren_op OR wrdi_op); PROCESS (ncs_wire) BEGIN IF (ncs_wire = '1' AND ncs_wire'event) THEN IF (wrsr_op = '1') THEN dffe36a <= ( dffe37a(3 DOWNTO 2)); END IF; END IF; END PROCESS; PROCESS (sck_wire) BEGIN IF (sck_wire = '1' AND sck_wire'event) THEN IF (wire_dffe37a_ena(0) = '1') THEN dffe37a(0) <= wire_dffe37a_d(0); END IF; END IF; END PROCESS; PROCESS (sck_wire) BEGIN IF (sck_wire = '1' AND sck_wire'event) THEN IF (wire_dffe37a_ena(1) = '1') THEN dffe37a(1) <= wire_dffe37a_d(1); END IF; END IF; END PROCESS; PROCESS (sck_wire) BEGIN IF (sck_wire = '1' AND sck_wire'event) THEN IF (wire_dffe37a_ena(2) = '1') THEN dffe37a(2) <= wire_dffe37a_d(2); END IF; END IF; END PROCESS; PROCESS (sck_wire) BEGIN IF (sck_wire = '1' AND sck_wire'event) THEN IF (wire_dffe37a_ena(3) = '1') THEN dffe37a(3) <= wire_dffe37a_d(3); END IF; END IF; END PROCESS; wire_dffe37a_d <= ( dffe37a(2 DOWNTO 0) & si_wire); loop62 : FOR i IN 0 TO 3 GENERATE wire_dffe37a_ena(i) <= wire_w_lg_w_lg_w_lg_ncs_wire2w262w263w(0); END GENERATE loop62; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe38 <= '0'; ELSIF (sck_wire = '1' AND sck_wire'event) THEN IF (ncs_wire = '0') THEN dffe38 <= op_complete; END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe39 <= '0'; ELSIF (sck_wire = '1' AND sck_wire'event) THEN IF (ncs_wire = '0') THEN dffe39 <= (wire_cntr3_w_lg_w_q_range8w274w(0) AND wire_cntr3_q(2)); END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe4 <= '0'; ELSIF (sck_wire = '1' AND sck_wire'event) THEN IF (ncs_wire = '0') THEN dffe4 <= op_complete; END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe40a(0) <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (wire_dffe40a_ena(0) = '1') THEN dffe40a(0) <= wire_dffe40a_d(0); END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe40a(1) <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (wire_dffe40a_ena(1) = '1') THEN dffe40a(1) <= wire_dffe40a_d(1); END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe40a(2) <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (wire_dffe40a_ena(2) = '1') THEN dffe40a(2) <= wire_dffe40a_d(2); END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe40a(3) <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (wire_dffe40a_ena(3) = '1') THEN dffe40a(3) <= wire_dffe40a_d(3); END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe40a(4) <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (wire_dffe40a_ena(4) = '1') THEN dffe40a(4) <= wire_dffe40a_d(4); END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe40a(5) <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (wire_dffe40a_ena(5) = '1') THEN dffe40a(5) <= wire_dffe40a_d(5); END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe40a(6) <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (wire_dffe40a_ena(6) = '1') THEN dffe40a(6) <= wire_dffe40a_d(6); END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe40a(7) <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (wire_dffe40a_ena(7) = '1') THEN dffe40a(7) <= wire_dffe40a_d(7); END IF; END IF; END PROCESS; wire_dffe40a_d <= ( wire_dffe40a_w_lg_w_lg_w_q_range316w322w323w & wire_dffe40a_w_lg_w_q_range313w315w & wire_dffe40a_w_lg_w_q_range310w312w & wire_dffe40a_w_lg_w_q_range307w309w & wire_w_lg_w_lg_bp1_state305w306w & wire_w_lg_w_lg_bp0_state300w301w & wire_w_lg_w_lg_wen_state295w296w & wire_dffe40a_w_lg_w_q_range287w290w); loop63 : FOR i IN 0 TO 7 GENERATE wire_dffe40a_ena(i) <= wire_w_lg_w_lg_ncs_wire2w286w(0); END GENERATE loop63; wire_dffe40a_w_lg_w_lg_w_q_range287w338w339w(0) <= wire_dffe40a_w_lg_w_q_range287w338w(0) AND op_complete; wire_dffe40a_w_lg_w_q_range292w294w(0) <= wire_dffe40a_w_q_range292w(0) AND wire_w_lg_op_code6289w(0); wire_dffe40a_w_lg_w_q_range297w299w(0) <= wire_dffe40a_w_q_range297w(0) AND wire_w_lg_op_code6289w(0); wire_dffe40a_w_lg_w_q_range302w304w(0) <= wire_dffe40a_w_q_range302w(0) AND wire_w_lg_op_code6289w(0); wire_dffe40a_w_lg_w_q_range307w309w(0) <= wire_dffe40a_w_q_range307w(0) AND wire_w_lg_op_code6289w(0); wire_dffe40a_w_lg_w_q_range310w312w(0) <= wire_dffe40a_w_q_range310w(0) AND wire_w_lg_op_code6289w(0); wire_dffe40a_w_lg_w_q_range313w315w(0) <= wire_dffe40a_w_q_range313w(0) AND wire_w_lg_op_code6289w(0); wire_dffe40a_w_lg_w_q_range316w322w(0) <= wire_dffe40a_w_q_range316w(0) AND wire_w_lg_streg_complete321w(0); wire_dffe40a_w_lg_w_q_range287w290w(0) <= wire_dffe40a_w_q_range287w(0) AND wire_w_lg_op_code6289w(0); wire_dffe40a_w_lg_w_q_range287w338w(0) <= wire_dffe40a_w_q_range287w(0) AND rdsr_op; wire_dffe40a_w_lg_w_lg_w_q_range316w322w323w(0) <= wire_dffe40a_w_lg_w_q_range316w322w(0) OR wire_w_lg_w_lg_w_lg_ufm_busy318w319w320w(0); wire_dffe40a_w_q_range292w(0) <= dffe40a(0); wire_dffe40a_w_q_range297w(0) <= dffe40a(1); wire_dffe40a_w_q_range302w(0) <= dffe40a(2); wire_dffe40a_w_q_range307w(0) <= dffe40a(3); wire_dffe40a_w_q_range310w(0) <= dffe40a(4); wire_dffe40a_w_q_range313w(0) <= dffe40a(5); wire_dffe40a_w_q_range316w(0) <= dffe40a(6); wire_dffe40a_w_q_range287w(0) <= dffe40a(7); PROCESS (sck_wire) BEGIN IF (sck_wire = '1' AND sck_wire'event) THEN IF (wire_dffe41_ena = '1') THEN dffe41 <= si_wire; END IF; END IF; END PROCESS; wire_dffe41_ena <= (wire_w_lg_ncs_wire2w(0) AND ((((NOT wire_cntr11_q(0)) AND wire_cntr11_q(1)) AND wire_cntr11_q(2)) AND (NOT wire_cntr11_q(3)))); PROCESS (sck_wire) BEGIN IF (sck_wire = '1' AND sck_wire'event) THEN IF (wire_dffe42_ena = '1') THEN dffe42 <= si_wire; END IF; END IF; END PROCESS; wire_dffe42_ena <= (wire_w_lg_ncs_wire2w(0) AND (((wire_cntr11_q(0) AND wire_cntr11_q(1)) AND wire_cntr11_q(2)) AND (NOT wire_cntr11_q(3)))); PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe5a(0) <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (wire_dffe5a_ena(0) = '1') THEN dffe5a(0) <= wire_dffe5a_d(0); END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe5a(1) <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (wire_dffe5a_ena(1) = '1') THEN dffe5a(1) <= wire_dffe5a_d(1); END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe5a(2) <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (wire_dffe5a_ena(2) = '1') THEN dffe5a(2) <= wire_dffe5a_d(2); END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe5a(3) <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (wire_dffe5a_ena(3) = '1') THEN dffe5a(3) <= wire_dffe5a_d(3); END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe5a(4) <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (wire_dffe5a_ena(4) = '1') THEN dffe5a(4) <= wire_dffe5a_d(4); END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe5a(5) <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (wire_dffe5a_ena(5) = '1') THEN dffe5a(5) <= wire_dffe5a_d(5); END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe5a(6) <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (wire_dffe5a_ena(6) = '1') THEN dffe5a(6) <= wire_dffe5a_d(6); END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe5a(7) <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (wire_dffe5a_ena(7) = '1') THEN dffe5a(7) <= wire_dffe5a_d(7); END IF; END IF; END PROCESS; wire_dffe5a_d <= ( dffe5a(6 DOWNTO 0) & dffe6); loop75 : FOR i IN 0 TO 7 GENERATE wire_dffe5a_ena(i) <= wire_w_lg_w_lg_w_lg_w_lg_ncs_wire2w14w15w16w(0); END GENERATE loop75; PROCESS (sck_wire) BEGIN IF (sck_wire = '1' AND sck_wire'event) THEN IF (ncs_wire = '0') THEN dffe6 <= si; END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe7a(0) <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (wire_dffe7a_ena(0) = '1') THEN dffe7a(0) <= wire_dffe7a_d(0); END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe7a(1) <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (wire_dffe7a_ena(1) = '1') THEN dffe7a(1) <= wire_dffe7a_d(1); END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe7a(2) <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (wire_dffe7a_ena(2) = '1') THEN dffe7a(2) <= wire_dffe7a_d(2); END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe7a(3) <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (wire_dffe7a_ena(3) = '1') THEN dffe7a(3) <= wire_dffe7a_d(3); END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe7a(4) <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (wire_dffe7a_ena(4) = '1') THEN dffe7a(4) <= wire_dffe7a_d(4); END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe7a(5) <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (wire_dffe7a_ena(5) = '1') THEN dffe7a(5) <= wire_dffe7a_d(5); END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe7a(6) <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (wire_dffe7a_ena(6) = '1') THEN dffe7a(6) <= wire_dffe7a_d(6); END IF; END IF; END PROCESS; PROCESS (sck_wire, circuit_reset) BEGIN IF (circuit_reset = '1') THEN dffe7a(7) <= '0'; ELSIF (sck_wire = '0' AND sck_wire'event) THEN IF (wire_dffe7a_ena(7) = '1') THEN dffe7a(7) <= wire_dffe7a_d(7); END IF; END IF; END PROCESS; wire_dffe7a_d <= ( dffe7a(6 DOWNTO 0) & dffe8); loop76 : FOR i IN 0 TO 7 GENERATE wire_dffe7a_ena(i) <= wire_w_lg_w_lg_w_lg_ncs_wire2w14w15w(0); END GENERATE loop76; PROCESS (sck_wire) BEGIN IF (sck_wire = '1' AND sck_wire'event) THEN IF (ncs_wire = '0') THEN dffe8 <= si; END IF; END IF; END PROCESS; PROCESS (sck_wire) BEGIN IF (sck_wire = '1' AND sck_wire'event) THEN IF (ncs_wire = '0') THEN dffe9 <= (((op_complete_state AND read_op) AND wire_w_lg_ufm_busy75w(0)) AND wire_w_lg_ufm_bgpbusy12w(0)); END IF; END IF; END PROCESS; wire_cntr11_clk_en <= wire_w_lg_w_lg_w_lg_ncs_wire2w80w81w(0); wire_w_lg_w_lg_w_lg_ncs_wire2w80w81w(0) <= (wire_w_lg_ncs_wire2w(0) AND wire_w_lg_addr_complete79w(0)) AND addr_state; cntr11 : lpm_counter GENERIC MAP ( lpm_direction => "UP", lpm_port_updown => "PORT_UNUSED", lpm_width => 4 ) PORT MAP ( aclr => circuit_reset, clk_en => wire_cntr11_clk_en, clock => sck_wire, q => wire_cntr11_q ); wire_cntr14_w_lg_w_q_range92w199w(0) <= wire_cntr14_w_q_range92w(0) AND read_op_state; wire_cntr14_clk_en <= wire_w_lg_w_lg_ncs_wire2w213w(0); wire_w_lg_w_lg_ncs_wire2w213w(0) <= wire_w_lg_ncs_wire2w(0) AND ((read_op AND data_state) OR wire_w_lg_w_lg_write_op209w210w(0)); wire_cntr14_w_q_range92w(0) <= wire_cntr14_q(3); cntr14 : lpm_counter GENERIC MAP ( lpm_direction => "UP", lpm_port_updown => "PORT_UNUSED", lpm_width => 4 ) PORT MAP ( aclr => circuit_reset, clk_en => wire_cntr14_clk_en, clock => sck_wire, q => wire_cntr14_q ); wire_cntr3_w_lg_w_q_range8w274w(0) <= wire_cntr3_w_q_range8w(0) AND wire_cntr3_w_lg_w_q_range7w273w(0); wire_cntr3_w_lg_w_q_range7w273w(0) <= NOT wire_cntr3_w_q_range7w(0); wire_cntr3_clk_en <= wire_w_lg_w_lg_w_lg_ncs_wire2w5w6w(0); wire_w_lg_w_lg_w_lg_ncs_wire2w5w6w(0) <= (wire_w_lg_ncs_wire2w(0) AND wire_w_lg_op_complete3w(0)) AND op_state; wire_cntr3_clock <= wire_w_lg_sck_wire1w(0); wire_cntr3_w_q_range8w(0) <= wire_cntr3_q(0); wire_cntr3_w_q_range7w(0) <= wire_cntr3_q(1); cntr3 : lpm_counter GENERIC MAP ( lpm_direction => "UP", lpm_port_updown => "PORT_UNUSED", lpm_width => 3 ) PORT MAP ( aclr => circuit_reset, clk_en => wire_cntr3_clk_en, clock => wire_cntr3_clock, q => wire_cntr3_q ); maxii_ufm_block1 : maxii_ufm GENERIC MAP ( ADDRESS_WIDTH => 9, ERASE_TIME => 500000000, INIT_FILE => "none", mem1 => "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111", mem10 => "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111", mem11 => "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111", mem12 => "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111", mem13 => "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111", mem14 => "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111", mem15 => "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111", mem16 => "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111", mem2 => "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111", mem3 => "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111", mem4 => "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111", mem5 => "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111", mem6 => "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111", mem7 => "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111", mem8 => "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111", mem9 => "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111", OSC_SIM_SETTING => 180000, PROGRAM_TIME => 1600000 ) PORT MAP ( arclk => ufm_arclk, ardin => ufm_ardin, arshft => ufm_arshft, bgpbusy => wire_maxii_ufm_block1_bgpbusy, busy => wire_maxii_ufm_block1_busy, drclk => ufm_drclk, drdin => ufm_drdin, drdout => wire_maxii_ufm_block1_drdout, drshft => ufm_drshft, erase => ufm_erase, osc => wire_maxii_ufm_block1_osc, oscena => ufm_oscena, program => ufm_program ); wire_tri_buf15_out <= (wire_w_lg_w_lg_ufm_drdout340w341w(0) OR wire_dffe40a_w_lg_w_lg_w_q_range287w338w339w(0)) WHEN wire_tri_buf15_oe = '1' ELSE 'Z'; wire_tri_buf15_in <= (wire_w_lg_w_lg_ufm_drdout340w341w(0) OR wire_dffe40a_w_lg_w_lg_w_q_range287w338w339w(0)); wire_tri_buf15_oe <= (((rdsr_op AND op_complete) OR ((read_op AND read_op_state) AND wire_w_lg_data_state344w(0))) AND wire_w_lg_ncs_wire2w(0)); END RTL; --ufm_pack_altufm_spi_6ph --VALID FILE LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY ufm_pack IS PORT ( ncs : IN STD_LOGIC ; sck : IN STD_LOGIC ; si : IN STD_LOGIC ; so : OUT STD_LOGIC ); END ufm_pack; ARCHITECTURE RTL OF ufm_pack IS ATTRIBUTE synthesis_clearbox: boolean; ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS TRUE; SIGNAL sub_wire0 : STD_LOGIC ; COMPONENT ufm_pack_altufm_spi_6ph PORT ( sck : IN STD_LOGIC ; ncs : IN STD_LOGIC ; si : IN STD_LOGIC ; so : OUT STD_LOGIC ); END COMPONENT; BEGIN so <= sub_wire0; ufm_pack_altufm_spi_6ph_component : ufm_pack_altufm_spi_6ph PORT MAP ( sck => sck, ncs => ncs, si => si, so => sub_wire0 ); END RTL; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX II" -- Retrieval info: PRIVATE: INTENDED_DEVICE_PART STRING "" -- Retrieval info: PRIVATE: INTERFACE_CHOICE NUMERIC "2" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "0" -- Retrieval info: CONSTANT: ACCESS_MODE STRING "READ_WRITE" -- Retrieval info: CONSTANT: CONFIG_MODE STRING "EXTENDED" -- Retrieval info: CONSTANT: ERASE_TIME NUMERIC "500000000" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX II" -- Retrieval info: CONSTANT: LPM_FILE STRING "UNUSED" -- Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000" -- Retrieval info: CONSTANT: PROGRAM_TIME NUMERIC "1600000" -- Retrieval info: CONSTANT: WIDTH_UFM_ADDRESS NUMERIC "9" -- Retrieval info: USED_PORT: ncs 0 0 0 0 INPUT NODEFVAL ncs -- Retrieval info: USED_PORT: sck 0 0 0 0 INPUT NODEFVAL sck -- Retrieval info: USED_PORT: si 0 0 0 0 INPUT NODEFVAL si -- Retrieval info: USED_PORT: so 0 0 0 0 OUTPUT NODEFVAL so -- Retrieval info: CONNECT: @si 0 0 0 0 si 0 0 0 0 -- Retrieval info: CONNECT: @sck 0 0 0 0 sck 0 0 0 0 -- Retrieval info: CONNECT: @ncs 0 0 0 0 ncs 0 0 0 0 -- Retrieval info: CONNECT: so 0 0 0 0 @so 0 0 0 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL ufm_pack.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ufm_pack.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ufm_pack.cmp FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ufm_pack.bsf FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ufm_pack_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera -- Retrieval info: LIB_FILE: altera_mf -- Retrieval info: LIB_FILE: lpm -- Retrieval info: LIB_FILE: maxii