library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use IEEE.std_logic_arith.all;
use work.usefuls.all;
 
entity top_test is
end top_test;
 
architecture behavior of top_test is 
 
  -- Component Declaration for the Unit Under Test (UUT)
 
  component top
    port (
        -- Global
        sysclk : in std_logic; -- 60MHz
        power_good : in std_logic;
        reset_n : in std_logic;
        ext_reset_n : out std_logic;
        led : out std_logic_vector(1 downto 0);
        
        -- LEA-4T/6T
        gps_uart_rx : out std_logic;
        gps_uart_tx : in std_logic;
        gps_1pps : in std_logic;
        gps_1pps2 : in std_logic;
        gps_int0 : out std_logic;
        
        -- HMC5843
        mag_scl : inout std_logic;
        mag_sda : inout std_logic;
        
        -- ADS1248
        adc_start : out std_logic;
        adc_cs_n : out std_logic;
        adc_drdy_n : in std_logic;
        adc_dout : in std_logic;
        adc_din : out std_logic;
        adc_sclk : out std_logic;
        adc_reset_n : out std_logic;
      
        -- SPIROM
        spirom_sck : out std_logic;
        spirom_si : out std_logic;
        spirom_so : in std_logic;
        spirom_cs_n : out std_logic;
      
        -- Servo
        servo_in : in std_logic_vector(7 downto 0);
        servo_out : out std_logic_vector(7 downto 0);
        
        -- DSP (EMIFA)
        dsp_ema_d : inout std_logic_vector(7 downto 0);
        dsp_ema_a : in std_logic_vector(12 downto 0);
        dsp_ema_ba : in std_logic_vector(1 downto 0);
        dsp_ema_oe_n : in std_logic;
        dsp_ema_we_n : in std_logic;
        dsp_ema_wait: out std_logic;
        dsp_cs2_n : in std_logic;
        dsp_cs3_n : in std_logic;
        
        -- DSP(SPI0)
        dsp_spi0_simo_boot1 : inout std_logic;
        dsp_spi0_somi_boot0 : inout std_logic;
        dsp_spi0_clk_boot2 : inout std_logic;
        dsp_spi0_cs_n : in std_logic;
        
        -- DSP(I2C1)
        dsp_i2c1_sda_boot6 : inout std_logic;
        dsp_i2c1_scl_boot5 : inout std_logic;
        
        -- DSP(UART1)
        dsp_uart1_rxd : out std_logic;
        dsp_uart1_txd : in std_logic;
        
        -- DSP(UART2)
        dsp_uart2_rxd : out std_logic;
        dsp_uart2_txd : in std_logic;
        
        -- DSP(Boot) @see Boot loader Appendix.A
        dsp_boot3 : inout std_logic;
        dsp_boot7 : inout std_logic;
        
        -- Extrenal uart (XBee etc.)
        ext_uart_tx : in std_logic;
        ext_uart_rx : out std_logic;
      
        -- External spi slave (ADS etc.)
        ext_spi_slave_clk : out std_logic;
        ext_spi_slave_simo : out std_logic;
        ext_spi_slave_somi : in std_logic;
        ext_spi_slave_cs_n : out std_logic);
  end component;
  
  --clock
  signal sysclk : std_logic;
  signal gps_1pps : std_logic;

  signal reset : std_logic := '1';
  signal reset_n : std_logic;

  --DSP EMIFA
  signal dsp_ema_d : std_logic_vector(7 downto 0);
  signal dsp_ema_addr : std_logic_vector(14 downto 0);
  signal dsp_ema_oe_n : std_logic;
  signal dsp_ema_we_n : std_logic;
  signal dsp_cs3_n : std_logic;
  
  -- SPI0
  signal spi0_clk : std_logic;
  signal spi0_cs_n : std_logic := '1';
  signal spi0_mosi : std_logic := 'H';
  signal spi0_miso : std_logic := 'H';
  signal spi0_shift_reg : std_logic_vector(7 downto 0);
  
  -- Clock period definitions
  constant sysclk_f : time := (1000.0/60) * 1ns; -- 60MHz
  constant sysclk_h : time := sysclk_f / 2;
  constant extclk_f : time := 20ns; -- 50 MHz
  constant extclk_h : time := extclk_f / 2;
  constant spiclk_f : time := 200ns; -- 5 MHz
  constant spiclk_h : time := spiclk_f / 2;
  constant spiclk_q : time := spiclk_f / 4;
begin
 
  reset_n <= not reset;
 
  -- Instantiate the Unit Under Test (UUT)
  uut: top port map (
      -- Global
        sysclk => sysclk,
        power_good => '1',
        reset_n => reset_n,
        --ext_reset_n : out std_logic;
        --led : out std_logic_vector(1 downto 0);
        
        -- LEA-4T/6T
        --gps_uart_rx : out std_logic;
        gps_uart_tx => '1',
        gps_1pps => gps_1pps,
        gps_1pps2 => gps_1pps,
        --gps_int0 : out std_logic;
        
        -- HMC5843
        --mag_scl => 'Z',
        --mag_sda => 'Z',
        
        -- ADS1248
        --adc_start : out std_logic;
        --adc_cs_n : out std_logic;
        adc_drdy_n => '1',
        adc_dout => '1',
        --adc_din : out std_logic;
        --adc_sclk : out std_logic;
        --adc_reset_n : out std_logic;
      
        -- SPIROM
        --spirom_sck : out std_logic;
        --spirom_si : out std_logic;
        spirom_so => '1',
        --spirom_cs_n : out std_logic;
      
        -- Servo
        servo_in => (others => '0'),
        --servo_out : out std_logic_vector(7 downto 0);
        
        -- DSP (EMIFA)
        dsp_ema_d => dsp_ema_d,
        dsp_ema_a => dsp_ema_addr(14 downto 2),
        dsp_ema_ba => dsp_ema_addr(1 downto 0), 
        dsp_ema_oe_n => dsp_ema_oe_n,
        dsp_ema_we_n => dsp_ema_we_n,
        dsp_cs2_n => '1',
        dsp_cs3_n => dsp_cs3_n,
        
        -- DSP(SPI0)
        dsp_spi0_simo_boot1 => spi0_mosi,
        dsp_spi0_somi_boot0 => spi0_miso,
        dsp_spi0_clk_boot2 => spi0_clk,
        dsp_spi0_cs_n => spi0_cs_n,
        
        -- DSP(I2C1)
        --dsp_i2c1_sda_boot6 => 'Z',
        --dsp_i2c1_scl_boot5 => 'Z',
        
        -- DSP(UART1)
        --dsp_uart1_rxd : out std_logic;
        dsp_uart1_txd => '0',
        
        -- DSP(UART2)
        --dsp_uart2_rxd : out std_logic;
        dsp_uart2_txd => '0',
        
        -- DSP(Boot) @see Boot loader Appendix.A
        --dsp_boot3 => 'Z',
        --dsp_boot7 => 'Z'
        
        -- Extrenal uart (XBee etc.)
        ext_uart_tx => '1',
        -- ext_uart_rx => 'Z',
      
        -- External spi slave (ADS etc.)
        -- ext_spi_slave_clk => 'Z',
        -- ext_spi_slave_simo => 'Z',
        ext_spi_slave_somi => '1'
        -- ext_spi_slave_cs_n => 'Z',
        );

  -- Clock process definitions
  process_clk: process begin
    sysclk <= '0';
    wait for sysclk_h;
    sysclk <= '1';
    wait for sysclk_h;
  end process;
 
  process_1pps: process begin
    gps_1pps <= '1';
    wait for 10ms;
    gps_1pps <= '0';
    wait for (1sec - 10ms);
  end process;
  
  process_spiclk: process begin
    wait for 3us; -- wait for POR
    while true loop
      spi0_clk <= '0';
      wait for spiclk_h;
      spi0_clk <= '1';
      wait for spiclk_h;
    end loop;
  end process;

  -- Stimulus process
  process_stim: process begin
    -- START cond.
    dsp_ema_d <= (others => 'Z');
    dsp_ema_addr <= conv_std_logic_vector(16#10#, dsp_ema_addr'length); 
    dsp_ema_oe_n <= '1';
    dsp_ema_we_n <= '1';
    dsp_cs3_n <= '1';
  		
    -- hold reset state for 1000 clk cycles.
    wait for 1us;

    -- insert stimulus here
    reset <= '0';

    wait for 1us;
    
    -- setup
    dsp_cs3_n <= '0';
    wait for extclk_f * 3;
    
    -- strobe
    dsp_ema_oe_n <= '0';
    wait for extclk_f * 3;
    
    -- hold
    dsp_ema_oe_n <= '1';
    wait for extclk_f * 2;
    
    dsp_cs3_n <= '1';
    
    wait for extclk_f * 10;
    dsp_ema_d <= conv_std_logic_vector(16#A5#, dsp_ema_d'length);
    
    -- setup
    dsp_cs3_n <= '0';
    wait for extclk_f * 3;
    
    -- strobe
    dsp_ema_we_n <= '0';
    wait for extclk_f * 3;
    
    -- hold
    dsp_ema_we_n <= '1';
    wait for extclk_f * 2;
    
    dsp_cs3_n <= '1';
    
    dsp_ema_d <= (others => 'Z');
    wait for extclk_f * 10;
    
    -- setup
    dsp_cs3_n <= '0';
    wait for extclk_f * 3;
    
    -- strobe
    dsp_ema_oe_n <= '0';
    wait for extclk_f * 3;
    
    -- hold
    dsp_ema_oe_n <= '1';
    wait for extclk_f * 2;
    
    dsp_cs3_n <= '1';
    
    -- write to the general register(0)
    wait for extclk_f * 10;
    dsp_ema_addr <= conv_std_logic_vector(16#20#, dsp_ema_addr'length);
    dsp_ema_d <= conv_std_logic_vector(16#03#, dsp_ema_d'length);
    
    -- setup
    dsp_cs3_n <= '0';
    wait for extclk_f * 3;
    
    -- strobe
    dsp_ema_we_n <= '0';
    wait for extclk_f * 3;
    
    -- hold
    dsp_ema_we_n <= '1';
    wait for extclk_f * 2;
    
    dsp_cs3_n <= '1';
    
    -- read from the general register(0)
    wait for extclk_f * 10;
    dsp_ema_d <= (others => 'Z');
    
    -- setup
    dsp_cs3_n <= '0';
    wait for extclk_f * 3;
    
    -- strobe
    dsp_ema_oe_n <= '0';
    wait for extclk_f * 3;
    
    -- hold
    dsp_ema_oe_n <= '1';
    wait for extclk_f * 2;
    
    dsp_cs3_n <= '1';
    
    -- SPI test(R)
    wait for extclk_f * 10;
    wait until spi0_clk = '1';
    
    spi0_shift_reg <= conv_std_logic_vector(16#10#, spi0_shift_reg'length);
    wait for spiclk_q;
    spi0_cs_n <= '0';
    
    for i in spi0_shift_reg'range loop
      spi0_mosi <= spi0_shift_reg(spi0_shift_reg'high);
      wait for spiclk_h;
      spi0_shift_reg <= spi0_shift_reg(spi0_shift_reg'high - 1 downto 0) & spi0_miso;
      wait for spiclk_h;
    end loop;
    
    spi0_shift_reg <= conv_std_logic_vector(16#FF#, spi0_shift_reg'length);
    for j in 0 to 3 loop
      for i in spi0_shift_reg'range loop
        wait for spiclk_q;
        spi0_mosi <= spi0_shift_reg(spi0_shift_reg'high);
        wait for spiclk_h;
        wait for spiclk_q;
        spi0_shift_reg <= spi0_shift_reg(spi0_shift_reg'high - 1 downto 0) & spi0_miso;
      end loop;
    end loop;
    
    spi0_cs_n <= '1';
    
    -- SPI test(W)
    wait for extclk_f * 10;
    wait until spi0_clk = '1';
    
    spi0_shift_reg <= conv_std_logic_vector(16#90#, spi0_shift_reg'length);
    wait for spiclk_q;
    spi0_cs_n <= '0';
    
    for i in spi0_shift_reg'range loop
      spi0_mosi <= spi0_shift_reg(spi0_shift_reg'high);
      wait for spiclk_h;
      spi0_shift_reg <= spi0_shift_reg(spi0_shift_reg'high - 1 downto 0) & spi0_miso;
      wait for spiclk_h;
    end loop;
    
    for j in 0 to 3 loop
      wait for spiclk_q / 2;
      spi0_shift_reg <= conv_std_logic_vector(j + 1, spi0_shift_reg'length);
      for i in spi0_shift_reg'range loop
        if i /= spi0_shift_reg'high then
          wait for spiclk_q / 2;
        end if;
        wait for spiclk_q / 2;
        spi0_mosi <= spi0_shift_reg(spi0_shift_reg'high);
        wait for spiclk_h;
        wait for spiclk_q;
        spi0_shift_reg <= spi0_shift_reg(spi0_shift_reg'high - 1 downto 0) & spi0_miso;
      end loop;
    end loop;
    
    spi0_cs_n <= '1';

    wait;
  end process;

end;