library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use IEEE.std_logic_arith.all;
use work.usefuls.all;
 
entity spi2internal_test is
end spi2internal_test;
 
architecture behavior of spi2internal_test is 
 
  -- Component Declaration for the Unit Under Test (UUT)
  component SPI2Internal is
    generic (
      bus_width : integer := 8;
      address_width : integer := 8;
      spi_slave_devices : integer := 1);
    port (
      clk : in std_logic;
      
      -- external SPI
      spi_cs_n : in std_logic;
      spi_clk : in std_logic;
      spi_mosi : in std_logic;
      spi_miso : out std_logic;
      
      spi_slave_cs_n : out std_logic_vector(spi_slave_devices-1 downto 0);
      spi_slave_miso : in std_logic_vector(spi_slave_devices-1 downto 0);
      
      -- internal bus
      internal_cs : out std_logic;
      internal_m2d : out std_logic_vector(bus_width-1 downto 0);
      internal_d2m : in std_logic_vector(bus_width-1 downto 0);
      internal_dir : out std_logic;    -- master to device => '1', device to master => '0'
      internal_addr : out std_logic_vector(address_width - 1 downto 0);
      internal_done : in std_logic);  -- complete write / valid output
  end component;
  
  --clock
  signal sysclk : std_logic;
  
  -- Clock period definitions
  constant sysclk_f : time := (1000.0/60) * 1ns; -- 60MHz
  constant sysclk_h : time := sysclk_f / 2;
  constant spiclk_f : time := 200ns; -- 5 MHz
  constant spiclk_h : time := spiclk_f / 2;
  constant spiclk_q : time := spiclk_f / 4;
  
  signal spi_cs_n : std_logic := '1';
  signal spi_clk : std_logic := '1';
  signal spi_mosi : std_logic := '1';
  signal spi_miso : std_logic;
  
  constant spi_slave_devices : integer := 2;
  signal spi_slave_miso : std_logic_vector(spi_slave_devices - 1 downto 0) := "10";
  
  signal spi_shift_reg : std_logic_vector(7 downto 0);
  
  signal internal_d2m : std_logic_vector(7 downto 0) := (others => '1');
  signal internal_addr : std_logic_vector(5 downto 0);
  signal internal_done : std_logic := '1';
  
begin
  -- Instantiate the Unit Under Test (UUT)
  uut: SPI2Internal
    generic map (
      bus_width => internal_d2m'length,
      address_width => internal_addr'length,
      spi_slave_devices => spi_slave_devices)
    port map (
      clk=> sysclk,
      
      -- external SPI
      spi_cs_n => spi_cs_n, 
      spi_clk => spi_clk,
      spi_mosi => spi_mosi, 
      spi_miso => spi_miso,
      
      --spi_slave_cs_n => spi_slave_cs_n,
      spi_slave_miso => spi_slave_miso,
      
      -- internal bus
      --internal_cs => spi_active,
      --internal_m2d => internal_m2d,
      internal_d2m => internal_d2m,
      --internal_dir => internal_dir,
      internal_addr => internal_addr,
      internal_done=> internal_done);


  -- Clock process definitions
  process_clk: process begin
    sysclk <= '0';
    wait for sysclk_h;
    sysclk <= '1';
    wait for sysclk_h;
  end process;
  
  process_spiclk: process begin
    wait for 0.15us;
    
    while true loop
      spi_clk <= '0';
      wait for spiclk_h;
      spi_clk <= '1';
      wait for spiclk_h;
    end loop;
  end process;

  -- Stimulus process
  process_stim: process begin
    -- hold state
    wait for 0.1us;
    
    wait until spi_clk = '1';
    
    spi_shift_reg <= conv_std_logic_vector(16#FF#, spi_shift_reg'length);
    wait for spiclk_q;
    spi_cs_n <= '0';
    
    for i in spi_shift_reg'range loop
      spi_mosi <= spi_shift_reg(spi_shift_reg'high);
      wait for spiclk_h;
      spi_shift_reg <= spi_shift_reg(spi_shift_reg'high - 1 downto 0) & spi_miso;
      wait for spiclk_h;
    end loop;
    
    spi_shift_reg <= conv_std_logic_vector(16#A5#, spi_shift_reg'length);
    for i in spi_shift_reg'range loop
      wait for spiclk_q;
      spi_mosi <= spi_shift_reg(spi_shift_reg'high);
      wait for spiclk_h;
      wait for spiclk_q;
      spi_shift_reg <= spi_shift_reg(spi_shift_reg'high - 1 downto 0) & spi_miso;
    end loop;
    
    spi_cs_n <= '1';
    
    wait for 0.1us;
    
    wait until spi_clk = '1';
    
    spi_shift_reg <= conv_std_logic_vector(16#FE#, spi_shift_reg'length);
    wait for spiclk_q;
    spi_cs_n <= '0';
    
    for i in spi_shift_reg'range loop
      spi_mosi <= spi_shift_reg(spi_shift_reg'high);
      wait for spiclk_h;
      spi_shift_reg <= spi_shift_reg(spi_shift_reg'high - 1 downto 0) & spi_miso;
      wait for spiclk_h;
    end loop;
    
    spi_shift_reg <= conv_std_logic_vector(16#A5#, spi_shift_reg'length);
    for i in spi_shift_reg'range loop
      wait for spiclk_q;
      spi_mosi <= spi_shift_reg(spi_shift_reg'high);
      wait for spiclk_h;
      wait for spiclk_q;
      spi_shift_reg <= spi_shift_reg(spi_shift_reg'high - 1 downto 0) & spi_miso;
    end loop;
    
    spi_cs_n <= '1';

    wait;
  end process;

end;