library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.usefuls.ALL;

entity POR is
  generic (
      hold_count : natural := 1023);
  port (
      clk : in std_logic;
      reset_in : in std_logic;
      reset_out : out std_logic;
      reset_out_n : out std_logic);
end POR;

architecture Behavioral of POR is
  constant counter_bits : natural := min_bits(hold_count);
  signal counter : std_logic_vector(counter_bits - 1 downto 0) 
      := (others => '0');
  signal reset_out_buf : std_logic := '1';
begin
  process(clk, reset_in) begin
    if reset_in = '1' then
      counter <= (others => '0');
      reset_out_buf <= '1';
    elsif clk'event and clk = '1' then
      if counter < conv_std_logic_vector(hold_count, counter'length) then
        counter <= counter + 1;
        reset_out_buf <= '1';
      else
        counter <= counter;
        reset_out_buf <= '0';
      end if;
    end if;
  end process;
  reset_out <= reset_out_buf;
  reset_out_n <= not reset_out_buf;
end Behavioral;