library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.std_logic_arith.all; entity EMIFA2Internal is generic ( bus_width : integer := 8; address_width : integer := 8); port ( clk : in std_logic; -- external EMIFA emifa_data : inout std_logic_vector(bus_width-1 downto 0); emifa_address : in std_logic_vector(address_width-1 downto 0); emifa_oe_n : in std_logic; emifa_we_n : in std_logic; emifa_cs_n : in std_logic; emifa_wait : out std_logic; -- internal bus internal_cs : out std_logic; internal_m2d : out std_logic_vector(bus_width-1 downto 0); internal_d2m : in std_logic_vector(bus_width-1 downto 0); internal_dir : out std_logic; -- master to device => '1', device to master => '0' internal_addr : out std_logic_vector(address_width-1 downto 0); internal_done : in std_logic); -- complete write / valid output end EMIFA2Internal; architecture Behavioral of EMIFA2Internal is constant DIR_D2M : std_logic := '0'; constant DIR_M2D : std_logic := '1'; begin emifa_data <= internal_d2m when emifa_cs_n = '0' and emifa_oe_n = '0' else (others => 'Z'); emifa_wait <= not internal_done when emifa_cs_n = '0' and (emifa_we_n = '0' or emifa_oe_n = '0') else '0' when emifa_cs_n = '0' else 'Z'; process(clk) begin if clk'event and clk = '1' then if emifa_cs_n = '0' and emifa_oe_n = '0' then internal_cs <= '1'; internal_addr <= emifa_address; internal_dir <= DIR_D2M; internal_m2d <= (others => 'Z'); elsif emifa_cs_n = '0' and emifa_we_n = '0' then internal_cs <= '1'; internal_addr <= emifa_address; internal_dir <= DIR_M2D; internal_m2d <= emifa_data; else internal_cs <= '0'; internal_addr <= (others => 'Z'); internal_dir <= 'Z'; internal_m2d <= (others => 'Z'); end if; end if; end process; end Behavioral;