library IEEE;
use IEEE.STD_LOGIC_1164.all;

package ram_cs2_pkg is
  constant BUS_WIDTH : integer := 8; -- change if need
  constant ADDRESSES : integer := 64; -- change if need
    
  subtype bus_t is std_logic_vector(BUS_WIDTH - 1 downto 0);
  type memory_t is array (ADDRESSES - 1 downto 0) of bus_t;
end ram_cs2_pkg;