library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.usefuls.ALL;

entity Busmaster is
  generic (
      bus_width : integer := 8;
      address_width : integer := 8;
      spi_slave_devices : integer := 1);
  port (
      clk : in std_logic;
      
      -- external EMIFA
      emifa_data : inout std_logic_vector(bus_width-1 downto 0);
      emifa_address : in std_logic_vector(address_width-1 downto 0);
      emifa_oe_n : in std_logic;
      emifa_we_n : in std_logic;
      emifa_cs_n : in std_logic;
      emifa_wait : out std_logic;
      
      -- external SPI
      spi_cs_n : in std_logic;
      spi_clk : in std_logic;
      spi_mosi : in std_logic;
      spi_miso : out std_logic;
      
      spi_slave_cs_n : out std_logic_vector(spi_slave_devices-1 downto 0);
      spi_slave_miso : in std_logic_vector(spi_slave_devices-1 downto 0);
      
      -- internal bus IF
      internal_cs : out std_logic;
      internal_m2d : out std_logic_vector(bus_width-1 downto 0);
      internal_d2m : in std_logic_vector(bus_width-1 downto 0);
      internal_dir : out std_logic;    -- master to device => '1', device to master => '0'
      internal_addr : out std_logic_vector(address_width-1 downto 0);
      internal_done : in std_logic);  -- complete write / valid output
end Busmaster;

architecture Behavioral of Busmaster is

  signal emifa_active, spi_active : std_logic;
  
  component EMIFA2Internal is
    generic (
      bus_width : integer := 8;
      address_width : integer := 8);
    port (
      clk : in std_logic;
    
      -- external EMIFA
      emifa_data : inout std_logic_vector(bus_width-1 downto 0);
      emifa_address : in std_logic_vector(address_width-1 downto 0);
      emifa_oe_n : in std_logic;
      emifa_we_n : in std_logic;
      emifa_cs_n : in std_logic;
      emifa_wait : out std_logic;
      
      -- internal bus
      internal_cs : out std_logic;
      internal_m2d : out std_logic_vector(bus_width-1 downto 0);
      internal_d2m : in std_logic_vector(bus_width-1 downto 0);
      internal_dir : out std_logic;    -- master to device => '1', device to master => '0'
      internal_addr : out std_logic_vector(address_width-1 downto 0);
      internal_done : in std_logic);  -- complete write / valid output
  end component;
  
  component SPI2Internal is
    generic (
      bus_width : integer := 8;
      address_width : integer := 8;
      spi_slave_devices : integer := 1);
    port (
      clk : in std_logic;
      
      -- external SPI
      spi_cs_n : in std_logic;
      spi_clk : in std_logic;
      spi_mosi : in std_logic;
      spi_miso : out std_logic;
      
      spi_slave_cs_n : out std_logic_vector(spi_slave_devices-1 downto 0);
      spi_slave_miso : in std_logic_vector(spi_slave_devices-1 downto 0);
      
      -- internal bus
      internal_cs : out std_logic;
      internal_m2d : out std_logic_vector(bus_width-1 downto 0);
      internal_d2m : in std_logic_vector(bus_width-1 downto 0);
      internal_dir : out std_logic;    -- master to device => '1', device to master => '0'
      internal_addr : out std_logic_vector(address_width - 1 downto 0);
      internal_done : in std_logic);  -- complete write / valid output
  end component;
  
begin
  
  emifa : EMIFA2Internal
    generic map (
        bus_width => bus_width,
        address_width => address_width)
    port map (
        clk => clk,
        
        -- external EMIFA
        emifa_data => emifa_data,
        emifa_address => emifa_address,
        emifa_oe_n => emifa_oe_n,
        emifa_we_n => emifa_we_n,
        emifa_cs_n => emifa_cs_n,
        emifa_wait => emifa_wait,
      
        -- internal bus
        internal_cs => emifa_active,
        internal_m2d => internal_m2d,
        internal_d2m => internal_d2m,
        internal_dir => internal_dir,
        internal_addr => internal_addr,
        internal_done => internal_done);
        
  spi : SPI2Internal
    generic map (
      bus_width => bus_width,
      address_width => address_width,
      spi_slave_devices => spi_slave_devices)
    port map (
      clk=> clk,
      
      -- external SPI
      spi_cs_n => spi_cs_n, 
      spi_clk => spi_clk,
      spi_mosi => spi_mosi, 
      spi_miso => spi_miso,
      
      spi_slave_cs_n => spi_slave_cs_n,
      spi_slave_miso => spi_slave_miso,
      
      -- internal bus
      internal_cs => spi_active,
      internal_m2d => internal_m2d,
      internal_d2m => internal_d2m,
      internal_dir => internal_dir,
      internal_addr => internal_addr,
      internal_done=> internal_done);
  
  internal_cs <= emifa_active or spi_active;
  
end Behavioral;