/* ------------------------------------------------------------------------ * * * * TinyFeather.gel * * * * This GEL file is designed to be used in conjunction with * * CCStudio 3.3+ and the c6745 based EVM. * * * * ------------------------------------------------------------------------ */ /* ------------------------------------------------------------------------ * * * * StartUp( ) * * Setup Memory Map * * * * ------------------------------------------------------------------------ */ StartUp( ) { Setup_Memory_Map( ); } /* ------------------------------------------------------------------------ * * * * OnTargetConnect( ) * * Setup PinMux, Power, PLLs, SDRAM & EMIFs * * * * ------------------------------------------------------------------------ */ OnTargetConnect( ) { GEL_TextOut( "\nc6745 DSP Startup Sequence\n\n" ); Setup_System_Config( ); // Setup Pin Mux and other system module registers Setup_PLL(); // Setup PLL0 (456MHz DSP, 152MHz EMIFs) Setup_Psc_All_On( ); // Setup All Power Domains //Setup_EMIFA(); // Async EMIF Setup_EMIFB(); // Setup SDRAM GEL_TextOut( "\nStartup Complete.\n\n" ); } /* ------------------------------------------------------------------------ * * * * OnPreFileLoaded( ) * * This function is called automatically when the 'Load Program' * * Menu item is selected. * * * * ------------------------------------------------------------------------ */ OnPreFileLoaded( ) { /* * GEL_Reset() is used to deal with the worst case senario of * unknown target state. If for some reason a reset is not desired * upon target connection, GEL_Reset() may be removed and replaced * with something "less brutal" like a cache initialization * function. */ GEL_Reset( ); // Disable_EDMA( ); // Disable EDMA GEL_TextOut( "\n" ); } /* ------------------------------------------------------------------------ * * * * OnRestart( ) * * This function is called by CCS when you do Debug->Restart. * * The goal is to put the CPU into a known good state with respect to * * edma. * * Failure to do this can cause problems when you restart and * * run your application code multiple times. This is different * * then OnPreFileLoaded() which will do a GEL_Reset(). * * * * ------------------------------------------------------------------------ */ OnRestart( int nErrorCode ) { Disable_EDMA( ); // Disable EDMA GEL_TextOut( "\n" ); } menuitem "c6745 Memory Map"; /* ------------------------------------------------------------------------ * * * * Setup_Memory_Map( ) * * Setup the Memory Map for DSP. * * * * ------------------------------------------------------------------------ */ hotmenu Setup_Memory_Map( ) { GEL_MapOn( ); GEL_MapReset( ); /* DSP */ GEL_MapAddStr( 0x00700000, 0, 0x00100000, "R|W|AS4", 0 ); // DSP L2 ROM GEL_MapAddStr( 0x00800000, 0, 0x00040000, "R|W|AS4", 0 ); // DSP L2 RAM GEL_MapAddStr( 0x00E00000, 0, 0x00008000, "R|W|AS4", 0 ); // DSP L1P RAM GEL_MapAddStr( 0x00F00000, 0, 0x00008000, "R|W|AS4", 0 ); // DSP L1D RAM GEL_MapAddStr( 0x01800000, 0, 0x00010000, "R|W|AS4", 0 ); // DSP Interrupt Controller GEL_MapAddStr( 0x01810000, 0, 0x00001000, "R|W|AS4", 0 ); // DSP Powerdown Controller GEL_MapAddStr( 0x01811000, 0, 0x00001000, "R|W|AS4", 0 ); // DSP Security ID GEL_MapAddStr( 0x01812000, 0, 0x00001000, "R|W|AS4", 0 ); // DSP Revision ID GEL_MapAddStr( 0x01820000, 0, 0x00010000, "R|W|AS4", 0 ); // DSP EMC GEL_MapAddStr( 0x01830000, 0, 0x00010000, "R|W|AS4", 0 ); // DSP Internal Reserved GEL_MapAddStr( 0x01840000, 0, 0x00010000, "R|W|AS4", 0 ); // DSP Memory System GEL_MapAddStr( 0x11700000, 0, 0x00100000, "R|W|AS4", 0 ); // DSP L2 ROM (mirror) GEL_MapAddStr( 0x11800000, 0, 0x00040000, "R|W|AS4", 0 ); // DSP L2 RAM (mirror) GEL_MapAddStr( 0x11E00000, 0, 0x00008000, "R|W|AS4", 0 ); // DSP L1P RAM (mirror) GEL_MapAddStr( 0x11F00000, 0, 0x00008000, "R|W|AS4", 0 ); // DSP L1D RAM (mirror) /* Shared RAM */ //GEL_MapAddStr( 0x80000000, 0, 0x00020000, "R|W|AS4", 0 ); // Shared RAM /* EMIFA */ GEL_MapAddStr( 0x68000000, 0, 0x00008000, "R|W|AS4", 0 ); // EMIFA Control GEL_MapAddStr( 0x40000000, 0, 0x08000000, "R|W|AS4", 0 ); // EMIFA SDRAM Data (128MB) GEL_MapAddStr( 0x60000000, 0, 0x02000000, "R|W|AS4", 0 ); // AEMIF CS2 GEL_MapAddStr( 0x62000000, 0, 0x02000000, "R|W|AS4", 0 ); // AEMIF CS3 GEL_MapAddStr( 0x64000000, 0, 0x02000000, "R|W|AS4", 0 ); // AEMIF CS4 GEL_MapAddStr( 0x66000000, 0, 0x02000000, "R|W|AS4", 0 ); // AEMIF CS5 /* SDR SDRAM */ GEL_MapAddStr( 0xB0000000, 0, 0x00008000, "R|W|AS4", 0 ); // EMIFB Control GEL_MapAddStr( 0xC0000000, 0, 0x02000000, "R|W|AS4", 0 ); // EMIFB SDRAM Data (32MB) /* Peripherals */ GEL_MapAddStr( 0x01C00000, 0, 0x00008000, "R|W|AS4", 0 ); // EDMA3 CC GEL_MapAddStr( 0x01C08000, 0, 0x00000400, "R|W|AS4", 0 ); // EDMA3 TC0 GEL_MapAddStr( 0x01C08400, 0, 0x00000400, "R|W|AS4", 0 ); // EDMA3 TC1 GEL_MapAddStr( 0x01C10000, 0, 0x00001000, "R|W|AS4", 0 ); // PSC 0 GEL_MapAddStr( 0x01C11000, 0, 0x00001000, "R|W|AS4", 0 ); // PLL Controller 0 //GEL_MapAddStr( 0x01C12000, 0, 0x00001000, "R|W|AS4", 0 ); // Key Manager //GEL_MapAddStr( 0x01C13000, 0, 0x00001000, "R|W|AS4", 0 ); // Security Controller GEL_MapAddStr( 0x01C14000, 0, 0x00001000, "R|W|AS4", 0 ); // SYSCFG //GEL_MapAddStr( 0x01C16000, 0, 0x00001000, "R|W|AS4", 0 ); // IOPU 0 //GEL_MapAddStr( 0x01C17000, 0, 0x00001000, "R|W|AS4", 0 ); // IOPU 2 GEL_MapAddStr( 0x01C20000, 0, 0x00001000, "R|W|AS4", 0 ); // Timer64P 0 GEL_MapAddStr( 0x01C21000, 0, 0x00001000, "R|W|AS4", 0 ); // Timer64P 1 GEL_MapAddStr( 0x01C22000, 0, 0x00001000, "R|W|AS4", 0 ); // I2C 0 GEL_MapAddStr( 0x01C23000, 0, 0x00001000, "R|W|AS4", 0 ); // RTC //GEL_MapAddStr( 0x01C24000, 0, 0x00001000, "R|W|AS4", 0 ); // IOPU 1 //GEL_MapAddStr( 0x01C30000, 0, 0x00000200, "R|W|AS4", 0 ); // dMax Data RAM 0 //GEL_MapAddStr( 0x01C32000, 0, 0x00000200, "R|W|AS4", 0 ); // dMax Data RAM 1 //GEL_MapAddStr( 0x01C34000, 0, 0x00004000, "R|W|AS4", 0 ); // dMax Control Registers //GEL_MapAddStr( 0x01C38000, 0, 0x00001000, "R|W|AS4", 0 ); // dMAX MAX0 Config Memory //GEL_MapAddStr( 0x01C3C000, 0, 0x00001000, "R|W|AS4", 0 ); // dMAX MAX1 Config Memory GEL_MapAddStr( 0x01C40000, 0, 0x00001000, "R|W|AS4", 0 ); // MMC/SD 0 GEL_MapAddStr( 0x01C41000, 0, 0x00001000, "R|W|AS4", 0 ); // SPI 0 GEL_MapAddStr( 0x01C42000, 0, 0x00001000, "R|W|AS4", 0 ); // UART 0 //GEL_MapAddStr( 0x01C43000, 0, 0x00001000, "R|W|AS4", 0 ); // MPU 0 GEL_MapAddStr( 0x01D00000, 0, 0x00001000, "R|W|AS4", 0 ); // McASP 0 Control GEL_MapAddStr( 0x01D01000, 0, 0x00001000, "R|W|AS4", 0 ); // McASP 0 FIFO Ctrl GEL_MapAddStr( 0x01D02000, 0, 0x00001000, "R|W|AS4", 0 ); // McASP 0 Data GEL_MapAddStr( 0x01D04000, 0, 0x00001000, "R|W|AS4", 0 ); // McASP 1 Control GEL_MapAddStr( 0x01D05000, 0, 0x00001000, "R|W|AS4", 0 ); // McASP 1 FIFO Ctrl GEL_MapAddStr( 0x01D06000, 0, 0x00001000, "R|W|AS4", 0 ); // McASP 1 Data //GEL_MapAddStr( 0x01D08000, 0, 0x00001000, "R|W|AS4", 0 ); // McASP 2 Control //GEL_MapAddStr( 0x01D09000, 0, 0x00001000, "R|W|AS4", 0 ); // McASP 2 FIFO Ctrl //GEL_MapAddStr( 0x01D0A000, 0, 0x00001000, "R|W|AS4", 0 ); // McASP 2 Data GEL_MapAddStr( 0x01D0C000, 0, 0x00001000, "R|W|AS4", 0 ); // UART 1 GEL_MapAddStr( 0x01D0D000, 0, 0x00001000, "R|W|AS4", 0 ); // UART 2 GEL_MapAddStr( 0x01D0E000, 0, 0x00001000, "R|W|AS4", 0 ); // IOPU 4 GEL_MapAddStr( 0x01E00000, 0, 0x00010000, "R|W|AS4", 0 ); // USB0 (USB HS) Cfg GEL_MapAddStr( 0x01E10000, 0, 0x00001000, "R|W|AS4", 0 ); // UHPI Cfg //GEL_MapAddStr( 0x01E11000, 0, 0x00001000, "R|W|AS4", 0 ); // UHPI (IODFT) GEL_MapAddStr( 0x01E12000, 0, 0x00001000, "R|W|AS4", 0 ); // SPI 1 //GEL_MapAddStr( 0x01E13000, 0, 0x00001000, "R|W|AS4", 0 ); // LCD Controller GEL_MapAddStr( 0x01E14000, 0, 0x00001000, "R|W|AS4", 0 ); // MPU 1 GEL_MapAddStr( 0x01E15000, 0, 0x00001000, "R|W|AS4", 0 ); // MPU 2 GEL_MapAddStr( 0x01E20000, 0, 0x00002000, "R|W|AS4", 0 ); // EMAC CPPI port GEL_MapAddStr( 0x01E22000, 0, 0x00001000, "R|W|AS4", 0 ); // EMAC CPGMACSS registers GEL_MapAddStr( 0x01E23000, 0, 0x00001000, "R|W|AS4", 0 ); // EMAC CPGMAC registers GEL_MapAddStr( 0x01E24000, 0, 0x00001000, "R|W|AS4", 0 ); // EMAC MDIO port //GEL_MapAddStr( 0x01E25000, 0, 0x00001000, "R|W|AS4", 0 ); // USB1 (USB FS) GEL_MapAddStr( 0x01E26000, 0, 0x00001000, "R|W|AS4", 0 ); // GPIO GEL_MapAddStr( 0x01E27000, 0, 0x00001000, "R|W|AS4", 0 ); // PSC 1 GEL_MapAddStr( 0x01E28000, 0, 0x00001000, "R|W|AS4", 0 ); // I2C 1 //GEL_MapAddStr( 0x01E29000, 0, 0x00001000, "R|W|AS4", 0 ); // IOPU 3 //GEL_MapAddStr( 0x01E2A000, 0, 0x00001000, "R|W|AS4", 0 ); // PBIST Controller //GEL_MapAddStr( 0x01E2B000, 0, 0x00001000, "R|W|AS4", 0 ); // PBIST Combiner GEL_MapAddStr( 0x01F00000, 0, 0x00001000, "R|W|AS4", 0 ); // EPWM 0 GEL_MapAddStr( 0x01F01000, 0, 0x00001000, "R|W|AS4", 0 ); // HRPWM 0 GEL_MapAddStr( 0x01F02000, 0, 0x00001000, "R|W|AS4", 0 ); // EPWM 1 GEL_MapAddStr( 0x01F03000, 0, 0x00001000, "R|W|AS4", 0 ); // HRPWM 1 GEL_MapAddStr( 0x01F04000, 0, 0x00001000, "R|W|AS4", 0 ); // EPWM 2 GEL_MapAddStr( 0x01F05000, 0, 0x00001000, "R|W|AS4", 0 ); // HRPWM 2 GEL_MapAddStr( 0x01F06000, 0, 0x00001000, "R|W|AS4", 0 ); // ECAP 0 GEL_MapAddStr( 0x01F07000, 0, 0x00001000, "R|W|AS4", 0 ); // ECAP 1 GEL_MapAddStr( 0x01F08000, 0, 0x00001000, "R|W|AS4", 0 ); // ECAP 2 GEL_MapAddStr( 0x01F09000, 0, 0x00001000, "R|W|AS4", 0 ); // EQEP 0 GEL_MapAddStr( 0x01F0A000, 0, 0x00001000, "R|W|AS4", 0 ); // EQEP 1 GEL_MapAddStr( 0x01F0B000, 0, 0x00001000, "R|W|AS4", 0 ); // IOPU 5 } /* ------------------------------------------------------------------------ * * * * Clear_Memory_Map( ) * * Clear the Memory Map * * * * ------------------------------------------------------------------------ */ hotmenu Clear_Memory_Map( ) { GEL_MapOff( ); GEL_MapReset( ); } menuitem "C6745 Functions"; #define SYS_BASE 0x01C14000 #define REVID *(unsigned int*)(SYS_BASE + 0x000) #define DIEIDR0 *(unsigned int*)(SYS_BASE + 0x008) #define DIEIDR1 *(unsigned int*)(SYS_BASE + 0x00C) #define DIEIDR2 *(unsigned int*)(SYS_BASE + 0x010) #define DIEIDR3 *(unsigned int*)(SYS_BASE + 0x014) #define DEVIDR0 *(unsigned int*)(SYS_BASE + 0x018) //#define DEVIDR1 *(unsigned int*)(SYS_BASE + 0x01C) #define BOOTCFG *(unsigned int*)(SYS_BASE + 0x020) //#define CHIPREVIDR *(unsigned int*)(SYS_BASE + 0x024) #define KICK0R *(unsigned int*)(SYS_BASE + 0x038) #define KICK1R *(unsigned int*)(SYS_BASE + 0x03c) #define HOST0CFG *(unsigned int*)(SYS_BASE + 0x040) #define HOST1CFG *(unsigned int*)(SYS_BASE + 0x044) #define IRAWSTAT *(unsigned int*)(SYS_BASE + 0x0E0) #define IENSTAT *(unsigned int*)(SYS_BASE + 0x0E4) #define IENSET *(unsigned int*)(SYS_BASE + 0x0E8) #define IENCLR *(unsigned int*)(SYS_BASE + 0x0EC) #define EOI *(unsigned int*)(SYS_BASE + 0x0F0) #define FLTADDRR *(unsigned int*)(SYS_BASE + 0x0F4) #define FLTSTAT *(unsigned int*)(SYS_BASE + 0x0F8) #define MSTPRI0 *(unsigned int*)(SYS_BASE + 0x110) #define MSTPRI1 *(unsigned int*)(SYS_BASE + 0x114) #define MSTPRI2 *(unsigned int*)(SYS_BASE + 0x118) #define PINMUX0 *(unsigned int*)(SYS_BASE + 0x120) //PINMUX0 #define PINMUX1 *(unsigned int*)(SYS_BASE + 0x124) //PINMUX1 #define PINMUX2 *(unsigned int*)(SYS_BASE + 0x128) //PINMUX2 #define PINMUX3 *(unsigned int*)(SYS_BASE + 0x12C) //PINMUX3 #define PINMUX4 *(unsigned int*)(SYS_BASE + 0x130) //PINMUX4 #define PINMUX5 *(unsigned int*)(SYS_BASE + 0x134) //PINMUX5 #define PINMUX6 *(unsigned int*)(SYS_BASE + 0x138) //PINMUX6 #define PINMUX7 *(unsigned int*)(SYS_BASE + 0x13C) //PINMUX7 #define PINMUX8 *(unsigned int*)(SYS_BASE + 0x140) //PINMUX8 #define PINMUX9 *(unsigned int*)(SYS_BASE + 0x144) //PINMUX9 #define PINMUX10 *(unsigned int*)(SYS_BASE + 0x148) //PINMUX10 #define PINMUX11 *(unsigned int*)(SYS_BASE + 0x14C) //PINMUX11 #define PINMUX12 *(unsigned int*)(SYS_BASE + 0x150) //PINMUX12 #define PINMUX13 *(unsigned int*)(SYS_BASE + 0x154) //PINMUX13 #define PINMUX14 *(unsigned int*)(SYS_BASE + 0x158) //PINMUX14 #define PINMUX15 *(unsigned int*)(SYS_BASE + 0x15C) //PINMUX15 #define PINMUX16 *(unsigned int*)(SYS_BASE + 0x160) //PINMUX16 #define PINMUX17 *(unsigned int*)(SYS_BASE + 0x164) //PINMUX17 #define PINMUX18 *(unsigned int*)(SYS_BASE + 0x168) //PINMUX18 #define PINMUX19 *(unsigned int*)(SYS_BASE + 0x16C) //PINMUX19 #define SUSPSRC *(unsigned int*)(SYS_BASE + 0x170) #define CHIPSIG *(unsigned int*)(SYS_BASE + 0x174) #define CHIPSIG_CLR *(unsigned int*)(SYS_BASE + 0x178) #define CFGCHIP0 *(unsigned int*)(SYS_BASE + 0x17C) #define CFGCHIP1 *(unsigned int*)(SYS_BASE + 0x180) #define CFGCHIP2 *(unsigned int*)(SYS_BASE + 0x184) #define CFGCHIP3 *(unsigned int*)(SYS_BASE + 0x188) #define CFGCHIP4 *(unsigned int*)(SYS_BASE + 0x18C) #define PLL0_BASE 0x01C11000 /*SYSTEM PLL BASE ADDRESS*/ #define PLL0_REVID *(unsigned int*) (PLL0_BASE + 0x00) // PID //#define PLL0_FUSERR *(unsigned int*) (PLL0_BASE + 0xE0) // FuseFarm Error Reg #define PLL0_RSTYPE *(unsigned int*) (PLL0_BASE + 0xE4) // Reset Type status Reg #define PLL0_PLLCTL *(unsigned int*) (PLL0_BASE + 0x100) // PLL Control Register #define PLL0_OCSEL *(unsigned int*) (PLL0_BASE + 0x104) // OBSCLK Select Register //#define PLL0_SECCTL *(unsigned int*) (PLL0_BASE + 0x108) // PLL Secondary Control Register #define PLL0_PLLM *(unsigned int*) (PLL0_BASE + 0x110) // PLL Multiplier #define PLL0_PREDIV *(unsigned int*) (PLL0_BASE + 0x114) // Pre divider #define PLL0_PLLDIV1 *(unsigned int*) (PLL0_BASE + 0x118) // Diveder-1 #define PLL0_PLLDIV2 *(unsigned int*) (PLL0_BASE + 0x11C) // Diveder-2 #define PLL0_PLLDIV3 *(unsigned int*) (PLL0_BASE + 0x120) // Diveder-3 #define PLL0_OSCDIV1 *(unsigned int*) (PLL0_BASE + 0x124) // Oscilator Divider #define PLL0_POSTDIV *(unsigned int*) (PLL0_BASE + 0x128) // Post Divider //#define PLL0_BPDIV *(unsigned int*) (PLL0_BASE + 0x12C) // Bypass Divider //#define PLL0_WAKEUP *(unsigned int*) (PLL0_BASE + 0x130) // Wakeup Reg #define PLL0_PLLCMD *(unsigned int*) (PLL0_BASE + 0x138) // Command Reg #define PLL0_PLLSTAT *(unsigned int*) (PLL0_BASE + 0x13C) // Status Reg #define PLL0_ALNCTL *(unsigned int*) (PLL0_BASE + 0x140) // Clock Align Control Reg #define PLL0_DCHANGE *(unsigned int*) (PLL0_BASE + 0x144) // PLLDIV Ratio Chnage status #define PLL0_CKEN *(unsigned int*) (PLL0_BASE + 0x148) // Clock Enable Reg #define PLL0_CKSTAT *(unsigned int*) (PLL0_BASE + 0x14C) // Clock Status Reg #define PLL0_SYSTAT *(unsigned int*) (PLL0_BASE + 0x150) // Sysclk status reg #define PLL0_PLLDIV4 *(unsigned int*) (PLL0_BASE + 0x160) // Divider 4 #define PLL0_PLLDIV5 *(unsigned int*) (PLL0_BASE + 0x164) // Divider 5 #define PLL0_PLLDIV6 *(unsigned int*) (PLL0_BASE + 0x168) // Divider 6 #define PLL0_PLLDIV7 *(unsigned int*) (PLL0_BASE + 0x16C) // Divider 7 //#define PLL0_PLLDIV8 *(unsigned int*) (PLL0_BASE + 0x170) // Divider 8 //#define PLL0_PLLDIV9 *(unsigned int*) (PLL0_BASE + 0x174) // Divider 9 //#define PLL0_PLLDIV10 *(unsigned int*) (PLL0_BASE + 0x178) // Divider 10 //#define PLL0_PLLDIV11 *(unsigned int*) (PLL0_BASE + 0x17C) // Divider 11 //#define PLL0_PLLDIV12 *(unsigned int*) (PLL0_BASE + 0x180) // Divider 12 //#define PLL0_PLLDIV13 *(unsigned int*) (PLL0_BASE + 0x184) // Divider 13 //#define PLL0_PLLDIV14 *(unsigned int*) (PLL0_BASE + 0x188) // Divider 14 //#define PLL0_PLLDIV15 *(unsigned int*) (PLL0_BASE + 0x18C) // Divider 15 //#define PLL0_PLLDIV16 *(unsigned int*) (PLL0_BASE + 0x190) // Divider 16 #define PLLEN_MUX_SWITCH 4 #define PLL_LOCK_TIME_CNT 2400 /*PSC Module Related Registers*/ #define PSC0_BASE 0x01C10000 #define PSC1_BASE 0x01E27000 #define PSC0_MDCTL (PSC0_BASE+0xA00) #define PSC0_MDSTAT (PSC0_BASE+0x800) #define PSC0_PTCMD *(unsigned int*) (PSC0_BASE + 0x120) #define PSC0_PTSTAT *(unsigned int*) (PSC0_BASE + 0x128) #define PSC1_MDCTL (PSC1_BASE+0xA00) #define PSC1_MDSTAT (PSC1_BASE+0x800) #define PSC1_PTCMD *(unsigned int*) (PSC1_BASE + 0x120) #define PSC1_PTSTAT *(unsigned int*) (PSC1_BASE + 0x128) /*Enable Function for PSC0*/ PSC0_lPSC_enable(unsigned int PD, unsigned int LPSC_num) { *(unsigned int*) (PSC0_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC0_MDCTL+4*LPSC_num) & 0xFFFFFFE0) | 0x0003; PSC0_PTCMD = 0x1< 456 */ /* Configure DSP at 456MHz, EMIFs at 152MHz */ unsigned int CLKMODE = 0; unsigned int PLLM = 18; unsigned int POSTDIV = 0; unsigned int PLLDIV3 = 4; // 456/(4+1)=91.2 or 456/4.5 => EMIFA <= 100 unsigned int PLLDIV5 = 2; // 456/(2+1)=152 or 456/4.5 => EMIFB <= 152 unsigned int PLLDIV7 = 7; // Moved step 2c and 2d to step 0 /*Set PLLEN=0 and PLLRST=0, Reset the PLL*/ PLL0_PLLCTL &= 0xFFFFFFFE; /*PLL BYPASS MODE*/ /*wait for 4 cycles to allow PLLEN mux switches properly to bypass clock*/ for(i=0; i 91.2 MHz //CFGCHIP3 |= 0x1; // Select 4.5 divider for EMIFB clock source => 152 MHz GEL_TextOut( "PLL Setup Complete\n" ); } /* ------------------------------------------------------------------------ * * * * Disable_IRQ_Flush_Cache( ) * * Flush Cache & Disable Interrupts * * * * ------------------------------------------------------------------------ */ Disable_IRQ_Flush_Cache( ) { } /* ------------------------------------------------------------------------ * * * * Disable_EDMA( ) * * Disabe EDMA events and interrupts, clear any pending events * * * * ------------------------------------------------------------------------ */ Disable_EDMA( ) { #define EDMA_3CC_IECRH *( unsigned int* )( 0x01c0105c ) #define EDMA_3CC_EECRH *( unsigned int* )( 0x01c0102c ) #define EDMA_3CC_ICRH *( unsigned int* )( 0x01c01074 ) #define EDMA_3CC_ECRH *( unsigned int* )( 0x01c0100c ) #define EDMA_3CC_IECR *( unsigned int* )( 0x01c01058 ) #define EDMA_3CC_EECR *( unsigned int* )( 0x01c01028 ) #define EDMA_3CC_ICR *( unsigned int* )( 0x01c01070 ) #define EDMA_3CC_ECR *( unsigned int* )( 0x01c01008 ) GEL_TextOut( "Disable EDMA events\n" ); EDMA_3CC_IECRH = 0xffffffff; // IERH - Disable high interrupts EDMA_3CC_EECRH = 0xffffffff; // EERH - Disable high events EDMA_3CC_ICRH = 0xffffffff; // ICRH - Clear high interrupts EDMA_3CC_ECRH = 0xffffffff; // ICRH - Clear high events EDMA_3CC_IECR = 0xffffffff; // IER - Disable low interrupts EDMA_3CC_EECR = 0xffffffff; // EER - Disable low events EDMA_3CC_ICR = 0xffffffff; // ICR - Clear low interrupts EDMA_3CC_ECR = 0xffffffff; // ICRH - Clear low events } /* ------------------------------------------------------------------------ * * * * Enable_Instruction_Cache( ) * * Enable I-Cache * * * * ------------------------------------------------------------------------ */ hotmenu Enable_Instruction_Cache( ) { GEL_TextOut( "\Enable Instruction Cache.\n\n" ); CPSR = 0x400000d3; // Set to supervisor mode, disable IRQ/FIQ REG_CP15_I_CACHE = 1; // Enable Instruction Cache } /* ------------------------------------------------------------------------ * * * * Setup_System_Config( ) * * Configure PINMUX and other system module registers * * * * ------------------------------------------------------------------------ */ hotmenu Setup_System_Config( ) { GEL_TextOut( "Setup PINMUX Registers... " ); KICK0R = 0x83e70b13; // Kick0 register + data (unlock) KICK1R = 0x95a4f1e0; // Kick1 register + data (unlock) // sprufk4d.pdfの10.5.9 Pin Multiplexing Control Registersに記述あり PINMUX0 = 0x11112100; // EMIFB PINMUX1 = 0x11111111; // EMIFB PINMUX2 = 0x01111111; // EMIFB PINMUX3 = 0x00000000; PINMUX4 = 0x00000000; PINMUX5 = 0x11111110; // EMIFB PINMUX6 = 0x11111111; // EMIFB PINMUX7 = 0x11111111; // EMIFB, SPI0 /* PINMUX8 = 0x28822022; // UART2, GP5[11-10], I2C0, I2C1 PINMUX9 = 0x00000002; // UART2 PINMUX10 = 0x00000000; PINMUX11 = 0x11101100; // McASP1, UART1 PINMUX12 = 0x11111110; // McASP1 PINMUX13 = 0x11011111; // EMIFA / McASP1 / (SD) PINMUX14 = 0x00111111; // EMIFA / (SD) PINMUX15 = 0x11000000; // EMIFA / (SD) PINMUX16 = 0x11111111; // EMIFA / (SD) PINMUX17 = 0x00011111; // EMIFA PINMUX18 = 0x00111010; // EMIFA PINMUX19 = 0x00000001; // EMIFA */ // CHIP CONFIG 2 Register: Enable USB1 clock //CFGCHIP2 = 0x0000EB42; // USB0REF_FREQ=2 24MHz, USB0PHY_PLLON=1, USB0PHYPWDN=0, EB42 = 1110 1011 0100 0010 GEL_TextOut( "[Done]\n" ); } /* ------------------------------------------------------------------------ * * * * Setup_Psc_All_On( ) * * Enable all PSC modules on ALWAYSON and DSP power dominas. * * * * ------------------------------------------------------------------------ */ hotmenu Setup_Psc_All_On( ) { int i; GEL_TextOut( "Setup Power Modules (All on)... " ); // PSC0 PSC0_lPSC_enable(0, 0); PSC0_lPSC_enable(0, 1); PSC0_lPSC_enable(0, 2); PSC0_lPSC_enable(0, 3); // EMIFA PSC0_lPSC_enable(0, 4); PSC0_lPSC_enable(0, 5); PSC0_lPSC_enable(0, 6); PSC0_lPSC_enable(0, 8); PSC0_lPSC_enable(0, 9); PSC0_lPSC_enable(0, 10); PSC0_lPSC_enable(0, 11); PSC0_lPSC_enable(0, 12); PSC0_lPSC_enable(0, 13); // PSC1 PSC1_lPSC_enable(0, 1); PSC1_lPSC_enable(0, 2); PSC1_lPSC_enable(0, 3); PSC1_lPSC_enable(0, 4); PSC1_lPSC_enable(0, 5); PSC1_lPSC_enable(0, 6); // EMIFB PSC1_lPSC_enable(0, 7); PSC1_lPSC_enable(0, 8); PSC1_lPSC_enable(0, 9); PSC1_lPSC_enable(0, 10); PSC1_lPSC_enable(0, 11); PSC1_lPSC_enable(0, 12); PSC1_lPSC_enable(0, 13); PSC1_lPSC_enable(0, 16); PSC1_lPSC_enable(0, 17); PSC1_lPSC_enable(0, 20); PSC1_lPSC_enable(0, 21); PSC1_lPSC_enable(0, 24); PSC1_lPSC_enable(0, 25); PSC1_lPSC_enable(0, 26); PSC1_lPSC_enable(0, 31); GEL_TextOut( "[Done]\n" ); } /* ------------------------------------------------------------------------ * * * * Setup_EMIFA( ) * * Setup Async-EMIF to the specified timings using either NAND Hw * * controller or normal EMIF controller * * * * ------------------------------------------------------------------------ */ #define AEMIF_AWCCR *( unsigned int* )( 0x68000004 ) #define AEMIF_A1CR *( unsigned int* )( 0x68000010 ) #define AEMIF_A2CR *( unsigned int* )( 0x68000014 ) #define AEMIF_A3CR *( unsigned int* )( 0x68000018 ) #define AEMIF_A4CR *( unsigned int* )( 0x6800001C ) #define AEMIF_NANDFCR *( unsigned int* )( 0x68000060 ) Setup_EMIFA( ) { /* Use extended wait cycles to keep CE low during NAND access */ AEMIF_AWCCR = 0x300400ff; /* Setup CS2 - 8-bit NAND */ //AEMIF_A1CR = 0x00300388; //AEMIF_NANDFCR |= 1; /* Setup CS3 - 8-bit normal async */ AEMIF_A2CR = 0x4C5462B8; // RW => steup:3,strobe:5,hold:3 AEMIF_NANDFCR &= ~2; } /* ------------------------------------------------------------------------ * * * * Setup_EMIFB( ) * * Configure SDRAM. * * * * ------------------------------------------------------------------------ */ #define EMIFB_BASE 0xB0000000 #define EMIFB_SDSTAT *(unsigned int*)(EMIFB_BASE + 0x04) //SDRAM Status Register #define EMIFB_SDCFG *(unsigned int*)(EMIFB_BASE + 0x08) //SDRAM Bank Config Register #define EMIFB_SDREF *(unsigned int*)(EMIFB_BASE + 0x0C) //SDRAM Refresh Control Register #define EMIFB_SDTIM1 *(unsigned int*)(EMIFB_BASE + 0x10) //SDRAM Timing Register #define EMIFB_SDTIM2 *(unsigned int*)(EMIFB_BASE + 0x14) //SDRAM Timing Register Setup_EMIFB() { // MT48LC16M16A2P-6A:D TR SDRAM, 16M x 16 (16-bit data path), 152MHz (6.5ns) EMIFB_SDCFG = 0 // SDRAM Bank Config Register |( 1 << 15) // Unlock timing registers |( 1 << 14) // Narrow Mode (16bits wide) |( 3 << 9 ) // CAS latency is 3 |( 2 << 4 ) // 4 bank SDRAM devices |( 1 << 0 ); // 512-word pages requiring 9 column address bits EMIFB_SDREF = 0 // SDRAM Refresh Control Register |( 0 << 31) // Low power mode disabled |( 0 << 30) // MCLK stoping disabled |( 0 << 23) // Selects self refresh instead of power down |( 1187 << 0 ); // Refresh rate = 7812.5ns / 6.5ns EMIFB_SDTIM1 = 0 // SDRAM Timing Register 1 |( 9 << 25 ) // (60ns / 6.5ns) - 1 = TRFC @ 152MHz |( 2 << 22 ) // (18ns / 6.5ns) - 1 = TRP |( 2 << 19 ) // (18ns / 6.5ns) - 1 = TRCD |( 1 << 16 ) // (12.5ns / 6.5ns) - 1 = TWR |( 6 << 11 ) // (42ns / 6.5ns) - 1 = TRAS |( 9 << 6 ) // (60ns / 6.5ns) - 1 = TRC |( 1 << 3 ); // (12ns / 6.5ns) - 1 = TRRD EMIFB_SDTIM2 = 0 // SDRAM Timing Register 2 |( 14 << 27 ) // not sure how they got this number. the datasheet says value should be // "Maximum number of refresh_rate intervals from Activate to Precharge command" // but has no equation. TRASMAX is 120k. => 120000ns / 7812.5ns = 15.36 |( 10 << 16 ) // (67ns / 6.5ns) - 1 |( 6 << 0 ); // (45ns? / 6.5ns) - 1 }