library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use IEEE.std_logic_arith.all;

library work;
use work.usefuls.ALL;
 
entity top_test is
end top_test;
 
architecture behavior of top_test is 
 
  -- Clock period definitions
  constant clk_period_in_ns : integer := 21; -- [ns] 48 MHz
  constant clk_period : time := 1 ns * clk_period_in_ns;
  constant cam_dclk_period_in_ns : integer := 21 * 8;-- * 64; -- [ns]
  constant cam_dclk_period : time := 1 ns * cam_dclk_period_in_ns;
  
 
  -- Component Declaration for the Unit Under Test (UUT)
  component top is
    port (
        -- MCU(C8051F342) side
        sysclk : in std_logic;
        reset : in std_logic;      
        mcu_data : inout std_logic_vector(7 downto 0);
        mcu_dclk : in std_logic;
        mcu_req : in std_logic;
        mcu_ready : out std_logic;
        mcu_int_n : out std_logic;
        
        -- Camera side
        cam_extclk : out std_logic;
        cam_reset : out std_logic;
        cam_strobe : in std_logic;
        cam_dclk : in std_logic;
        cam_data : in std_logic_vector(7 downto 0);
        cam_hblk : in std_logic;
        cam_vblk : in std_logic;
        
        -- SDRAM side
        sdram_clk : out std_logic;
        sdram_cke : out std_logic;
        sdram_cs_n : out std_logic;
        sdram_we_n : out std_logic;
        sdram_cas_n : out std_logic;
        sdram_ras_n : out std_logic;
        sdram_dqm : out std_logic_vector(0 downto 0);
        sdram_bank_addr : out std_logic_vector(1 downto 0);
        sdram_addr : out std_logic_vector(11 downto 0);
        sdram_data : inout std_logic_vector(7 downto 0);
        
        -- Debug
        debug : out std_logic_vector(1 downto 0));
  end component;
  
  --I/O
  signal clk : std_logic;
  signal reset : std_logic := '1';
  
  signal mcu_data : std_logic_vector(7 downto 0); 
  signal mcu_dclk : std_logic;
  signal mcu_req : std_logic;
  signal mcu_ready : std_logic;
  
  signal cam_reset : std_logic;
  signal cam_strobe : std_logic;
  signal cam_dclk : std_logic;
  signal cam_data : std_logic_vector(7 downto 0) := conv_std_logic_vector(16#A5#, 8);
  signal cam_hblk : std_logic;
  signal cam_vblk : std_logic;
  
  signal sdram_data : std_logic_vector(7 downto 0);
  
  -- constants
  constant cam_hblk_length : integer := 512; -- 2560;
  constant cam_hblk_interval_length : integer := 440; -- 224;
  constant cam_vblk_length : integer := 2; --96; -- 1024;
  constant cam_vblk_interval_length : integer 
      := (cam_hblk_length + cam_hblk_interval_length) * 1; -- 3; --956; -- 28;
  
begin
 
  -- Instantiate the Unit Under Test
  UUT : top
      port map (
          -- MCU(C8051F342) side
          sysclk => clk,
          reset => reset,      
          mcu_data => mcu_data,
          mcu_dclk => mcu_dclk,
          mcu_req => mcu_req,
          mcu_ready => mcu_ready,
          --mcu_int_n => mcu_int_n,
          
          -- Camera side
          --cam_extclk => cam_extclk,
          cam_reset => cam_reset,
          cam_strobe => cam_strobe,
          cam_dclk => cam_dclk,
          cam_data => cam_data,
          cam_hblk => cam_hblk,
          cam_vblk => cam_vblk,
          
          -- SDRAM side
          --sdram_clk => sdram_clk,
          --sdram_cke => sdram_cke,
          --sdram_cs_n => sdram_cs_n,
          --sdram_we_n => sdram_we_n,
          --sdram_cas_n => sdram_cas_n,
          --sdram_ras_n => sdram_ras_n,
          --sdram_dqm => sdram_dqm,
          --sdram_bank_addr => sdram_bank_addr,
          --sdram_addr => sdram_addr,
          sdram_data => sdram_data); --,
          
          -- Debug
          --debug => debug);
  
  -- Clock process definitions
  clk_process :process begin
    clk <= '0';
    wait for clk_period/2;
    clk <= '1';
    wait for clk_period/2;
  end process;
  
  cam_dclk_process :process begin
    wait until cam_reset = '1';
    while true loop
      cam_dclk <= '0';
      wait for cam_dclk_period/2;
      cam_dclk <= '1';
      wait for cam_dclk_period/2;
    end loop;
  end process;
  
  cam_vblk_process : process begin
    wait until cam_reset = '1';
    cam_vblk <= '0';
    wait for 1 us;
    wait until cam_dclk = '0';
    while true loop
      cam_vblk <= '1';
      for i in 1 to cam_vblk_length loop
        if i > 1 then
          wait until cam_hblk = '1';  
        end if;
        wait until cam_hblk = '0';
      end loop;
      cam_vblk <= '0';
      for i in 1 to cam_vblk_interval_length loop
        wait until cam_dclk = '1';
        wait until cam_dclk = '0';
      end loop;
    end loop;
  end process;
  
  cam_hblk_process : process begin
    wait until cam_reset = '1';
    cam_hblk <= '0';
    while true loop
      wait until cam_vblk = '1';
      while cam_vblk = '1' loop
        for i in 1 to cam_hblk_length loop
          cam_hblk <= '1';
          wait until cam_dclk = '1' or cam_vblk /= '1';
          if cam_vblk /= '1' then
            exit;
          end if;
          wait until cam_dclk = '0' or cam_vblk /= '1';
          if cam_vblk /= '1' then
            exit;
          end if;
        end loop;
        for i in 1 to cam_hblk_interval_length loop
          cam_hblk <= '0';
          wait until cam_dclk = '1' or cam_vblk /= '1';
          if cam_vblk /= '1' then
            exit;
          end if;
          wait until cam_dclk = '0' or cam_vblk /= '1';
          if cam_vblk /= '1' then
            exit;
          end if;
        end loop;
      end loop;
    end loop;
  end process;
  
  mcu_dclk_process : process begin
    mcu_dclk <= '0';
    while true loop
      wait until mcu_ready = '1';
      wait for clk_period;
      while mcu_ready = '1' loop
        mcu_dclk <= '1';
        wait for clk_period;
        if mcu_ready /= '1' then
          wait until mcu_ready = '1';
        end if;
        wait for clk_period * 3;
        mcu_dclk <= '0';
        wait for clk_period;
      end loop;
    end loop;
  end process;
  
  mcu_req_process : process begin
    mcu_req <= '0';
    wait for 100 us;
    while true loop
      mcu_req <= '1';
      wait until mcu_ready = '1';
      wait until mcu_dclk = '0' and mcu_ready = '0';
      mcu_req <= '0';
      wait for 10 us; -- 100 us; -- 1000 us;
    end loop;
  end process;
  
  -- Stimulus process
  stim_proc: process begin
    -- hold reset state
    reset <= '1';
    wait for clk_period * 10;
    reset <= '0';
    wait for clk_period * 10;
    
    wait;
  end process;
end;