LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
USE ieee.numeric_std.ALL;

library work;
use work.usefuls.ALL;

entity divider_test is
end divider_test;
 
architecture behavior of divider_test is 
 
  -- Clock period definitions
  constant clk_period_in_ns : integer := 20; -- [ns] 50 MHz
  constant clk_period : time := 1 ns * clk_period_in_ns; 
 
  -- Component Declaration for the Unit Under Test (UUT)
  component DividerN is
    generic (
        divide_value : positive := 8);
    port (
        clk, reset : in std_logic;
        clk_out : out std_logic);
  end component;
  
  --I/O
  signal clk : std_logic;
  signal reset : std_logic := '1';
begin
 
  -- Instantiate the Unit Under Test
  UUT1 : DividerN
      generic map (
          divide_value => 7)
      port map (
          clk => clk,
          reset => reset);
  UUT2 : DividerN
      generic map (
          divide_value => 8)
      port map (
          clk => clk,
          reset => reset);
  
  -- Clock process definitions
  clk_process :process begin
    clk <= '0';
    wait for clk_period / 2;
    clk <= '1';
    wait for clk_period / 2;
  end process;
  
  -- Stimulus process
  stim_proc: process begin		
    -- hold reset state
    reset <= '1';
    wait for clk_period * 10;
    reset <= '0';
    wait for clk_period * 10;
    
    wait for 200 ns;
    
    wait;
  end process;
end;