library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use IEEE.std_logic_arith.all;

library work;
use work.usefuls.ALL;
 
entity SDRAM_test is
end SDRAM_test;
 
architecture behavior of SDRAM_test is 
 
  -- Clock period definitions
  constant clk_period_in_ns : integer := 20; -- [ns] 50 MHz
  constant clk_period : time := 1 ns * clk_period_in_ns; 
 
  -- Component Declaration for the Unit Under Test (UUT)
  component SDRAM is
    generic (
        address_width : integer := 24;
        data_width : integer := 16;
        sdram_dqm_width : integer := 2;
        sdram_bank_addr_width : integer := 2;
        sdram_addr_width : integer := 12;
        sdram_data_width : integer := 16;
        clk_period : integer := 25; -- [ns]
        sdram_refresh_cycle : integer := 15625;  -- [ns] 64 ms / 4096
        sdram_tRCD : integer := 18; -- [ns]
        sdram_tRFC : integer := 60; -- [ns]
        sdram_tRP : integer := 18; -- [ns]
        sdram_tWR : integer := 31; -- [ns]
        sdram_tMRD_clock : integer := 2;
        sdram_cas_latency : integer := 3);
    port (
        clk : in std_logic;
        
        -- Control side
        reset : in std_logic;
        cs : in std_logic;
        dir : in std_logic;   -- W => '1', R=> '0'
        done : out std_logic; -- complete write / data valid
        address : in std_logic_vector(
            address_width-1 downto 0);
        data_in : in std_logic_vector(
            data_width-1 downto 0);
        data_out : out std_logic_vector(
            data_width-1 downto 0);
        
        -- SDRAM side
        sdram_clk : out std_logic;
        sdram_cke : out std_logic;
        sdram_cs_n : out std_logic;
        sdram_we_n : out std_logic;
        sdram_cas_n : out std_logic;
        sdram_ras_n : out std_logic;
        sdram_dqm : out std_logic_vector(
            sdram_dqm_width-1 downto 0);
        sdram_bank_addr : out std_logic_vector(
            sdram_bank_addr_width-1 downto 0);
        sdram_addr : out std_logic_vector(
            sdram_addr_width-1 downto 0);
        sdram_data : inout std_logic_vector(
            sdram_data_width-1 downto 0));
  end component;
  
  --I/O
  signal clk : std_logic;
  signal reset : std_logic := '1';
  
  signal sdram_if_cs : std_logic;
  signal sdram_if_dir : std_logic;    -- W => '1', R => '0'
  signal sdram_if_done : std_logic;   -- complete write / data valid
  constant sdram_if_addr_width : integer := 23; -- 2^23 = 8M
  signal sdram_if_addr : std_logic_vector(sdram_if_addr_width-1 downto 0);
  constant sdram_if_data_width : integer := 8;
  signal sdram_if_data_in : std_logic_vector(sdram_if_data_width-1 downto 0);
  signal sdram_if_data_out : std_logic_vector(sdram_if_data_width-1 downto 0);
  
  constant sdram_data_width : integer := 8;
  signal sdram_data : std_logic_vector(sdram_data_width - 1 downto 0);
  
begin
 
  -- Instantiate the Unit Under Test
  UUT : SDRAM
      generic map (
          address_width => sdram_if_addr_width,
          data_width => sdram_if_data_width,
          sdram_dqm_width => 1,
          sdram_bank_addr_width => 2,
          sdram_addr_width => 12,
          sdram_data_width => sdram_data_width,
          clk_period => clk_period_in_ns, -- [ns]
          sdram_refresh_cycle => 15625, -- [ns]
          sdram_tRCD => 18, -- [ns]
          sdram_tRFC => 60, -- [ns]
          sdram_tRP => 18, -- [ns]
          sdram_tWR => 31, -- [ns]
          sdram_tMRD_clock => 2,
          sdram_cas_latency => 3)
      port map (
          clk => clk,
          
          -- Control side
          reset => reset,
          cs => sdram_if_cs,
          dir => sdram_if_dir,
          done => sdram_if_done, 
          address => sdram_if_addr,
          data_in => sdram_if_data_in,
          data_out => sdram_if_data_out,
          
          -- SDRAM side
          sdram_data => sdram_data);
  
  -- Clock process definitions
  clk_process :process begin
    clk <= '0';
    wait for clk_period/2;
    clk <= '1';
    wait for clk_period/2;
  end process;
  
  -- Stimulus process
  stim_proc: process begin		
    -- hold reset state
    reset <= '1';
    sdram_if_cs <= '0';
    wait for clk_period * 10;
    reset <= '0';
    wait for clk_period * 10;
    
    wait for 200 ns;
    
    sdram_if_dir <= '1';
    sdram_if_addr <= conv_std_logic_vector(0, sdram_if_addr_width);
    sdram_if_data_in <= conv_std_logic_vector(16#AA#, 8);
    sdram_if_cs <= '1';
    
    wait until sdram_if_done /= '0';
    wait for clk_period;
    
    sdram_if_cs <= '0';
    
    wait for clk_period * 2;
    
    sdram_if_dir <= '1';
    sdram_if_addr <= conv_std_logic_vector(1, sdram_if_addr_width);
    sdram_if_data_in <= conv_std_logic_vector(16#55#, 8);
    sdram_if_cs <= '1';
    
    wait until sdram_if_done /= '0';
    wait for clk_period;
    
    sdram_if_cs <= '0';
    
    wait for clk_period * 2;
    
    sdram_if_dir <= '0';
    sdram_if_addr <= conv_std_logic_vector(0, sdram_if_addr_width);
    sdram_if_cs <= '1';
    
    wait until sdram_if_done /= '0';
    wait for clk_period;
    
    sdram_if_cs <= '0';
    
    wait for clk_period * 2;
    
    sdram_if_dir <= '0';
    sdram_if_addr <= conv_std_logic_vector(1, sdram_if_addr_width);
    sdram_if_cs <= '1';
    
    wait until sdram_if_done /= '0';
    wait for clk_period;
    
    wait;
  end process;
end;