library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.std_logic_arith.all;

entity SmallRegister is
  generic (
      bits : integer := 8;
      reset_value : integer := 0);
  port (
      clk : in std_logic;
      data_in : in std_logic_vector(bits-1 downto 0);
      data_out : out std_logic_vector(bits-1 downto 0);
      dir : in std_logic;    -- write register => '1', read register => '0'
      cs : in std_logic;     -- chip select
      done : out std_logic;  -- complete write / valid output
      reset : in std_logic);
end SmallRegister;

architecture Behavioral of SmallRegister is
  signal data : std_logic_vector(bits-1 downto 0)
      := conv_std_logic_vector(reset_value, bits);
  signal cs_buf : std_logic;
  signal done_buf : std_logic;
begin
  process(clk) begin
    if clk'event and clk = '1' then
      cs_buf <= cs;
    end if;
  end process;
  
  process(clk, reset) begin
    if reset = '1' then
      data <= conv_std_logic_vector(reset_value, bits);
    elsif clk'event and clk = '1' then
      if cs_buf = '0' and cs = '1' and dir = '1' then
        data <= data_in;
      else null;
      end if;
    end if;
  end process;
  
  process(clk, cs) begin
    if cs = '0' then
      data_out <= (others => 'Z');
    elsif clk'event and clk = '1' then
      if cs_buf = '0' and cs = '1' and dir = '0' then
        data_out <= data;
      else null;
      end if;
    end if;
  end process;
  
  process(clk) begin
    if clk'event and clk = '1' then
      if cs = '1' then
        done_buf <= '1';
      else
        done_buf <= '0';
      end if;
    end if;
  end process;
  
  done <= done_buf when cs = '1' else 'Z';
end Behavioral;