library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use usefuls.all;

entity DividerN is
  generic (
      divide_value : integer := 8
    );
  port (
      clk_in, ce : in std_logic;
      clk_out, tc : out std_logic
    );
end DividerN;

architecture Behavioral of DividerN is
  constant required_bits : integer range 2 to integer'high
      := log2_ceil(divide_value-1);
  signal timer : std_logic_vector(required_bits - 1 downto 0) 
      := (others => '0');
begin
  process(clk_in, ce) begin
    if clk_in'event and clk_in = '1' then
      if ce = '1' then
        if timer = conv_std_logic_vector(divide_value-1, required_bits) then
          timer <= (others => '0');
          tc <= '1';
        else
          timer <= timer + 1;
          tc <= '0';
        end if;
      else
        timer <= timer;
        tc <= '0';
      end if;
    end if;
  end process;
  clk_out <= '1' when timer < conv_std_logic_vector(divide_value/2, required_bits) else '0';
end Behavioral;