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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:25:56 05/29/2008 
-- Design Name: 
-- Module Name:    i2c - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.std_logic_arith.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DEMUX is
  generic(
      address_width : integer := 8;
      num_demux : integer range 0 to (2 ** address_width) := 8;
      lowest_address : integer range 0 to ((2 ** address_width) - num_demux) := 0);
  port(
      address : in std_logic_vector(address_width - 1 downto 0);
      cs_in : in std_logic;
      cs_out : out std_logic_vector(num_demux - 1 downto 0));
end DEMUX;

architecture Behavioral of DEMUX is
  constant highest_address : integer := lowest_address + num_demux;
begin
  gen_cs : for i in 0 to num_demux - 1 generate
		process(address, cs_in) begin
		  if address = conv_std_logic_vector(i + lowest_address, address_width) then
		    cs_out(i) <= cs_in;
		  else
		    cs_out(i) <= '0';
		  end if;
		end process;
	end generate;
end Behavioral;