/*--------------------------------------------------------------*/ /* DSK6713.gel */ /* Version 3.00 */ /* */ /* This GEL file is designed to be used in conjunction with */ /* CCS 3.X and the TMS320C6713 based DSK. */ /* */ /*--------------------------------------------------------------*/ /*--------------------------------------------------------------*/ /* StartUp() */ /* This function is called each time CCS is started. */ /* Customize this function to perform desired initialization. */ /*--------------------------------------------------------------*/ StartUp() { setup_memory_map(); /*------------------------------------------------------*/ /* Uncomment the OnTargetConnect() call for CCS 2.X */ /* support. */ /* */ /* */ /*------------------------------------------------------*/ //OnTargetConnect(); } /*--------------------------------------------------------------*/ /* OnTargetConnect() */ /* This function is called by CCS when you do Debug->Connect on */ /* CCS 3.X. When using CCS 2.X, the OnTargetConnect() call */ /* should be uncommented from the StartUp() function. */ /*--------------------------------------------------------------*/ OnTargetConnect() { /*------------------------------------------------------*/ /* GEL_Reset() is used to deal with the worst case */ /* senario of unknown target state. If for some reason */ /* a reset is not desired upon target connection, */ /* GEL_Reset() may be removed and replaced with */ /* something "less brutal" like a cache initialization */ /* function. */ /*------------------------------------------------------*/ //GEL_Reset(); init_emif(); GEL_TextOut("GEL StartUp Complete.\n"); } /*--------------------------------------------------------------*/ /* OnReset() */ /* This function is called by CCS when you do Debug->Resest. */ /* The goal is to put the C6x into a known good state with */ /* respect to cache, edma and interrupts. */ /*--------------------------------------------------------------*/ OnReset( int nErrorCode ) { /*------------------------------------------------------*/ /* A debugger reset or GEL_Reset() does NOT reset the */ /* C6713 pll. Uncomment the following line if you want */ /* your pll reset. */ /*------------------------------------------------------*/ //reset_pll(); init_emif(); } /*--------------------------------------------------------------*/ /* OnPreFileLoaded() */ /* This function is called automatically when the 'Load Program'*/ /* Menu item is selected. */ /*--------------------------------------------------------------*/ OnPreFileLoaded() { /*------------------------------------------------------*/ /* GEL_Reset() is used to deal with the worst case */ /* senario of unknown target state. If for some reason */ /* a reset is not desired upon target connection, */ /* GEL_Reset() may be removed and replaced with */ /* something "less brutal" like a cache initialization */ /* function. */ /*------------------------------------------------------*/ GEL_Reset(); flush_cache(); IER = 0; IFR = 0; reset_pll(); // ROMブートではPLLの初期化をブートシーケンスでしてしまうので init_pll(); init_emif(); } /*--------------------------------------------------------------*/ /* OnRestart() */ /* This function is called by CCS when you do Debug->Restart. */ /* The goal is to put the C6x into a known good state with */ /* respect to cache, edma and interrupts. */ /* Failure to do this can cause problems when you restart and */ /* run your application code multiple times. This is different */ /* then OnPreFileLoaded() which will do a GEL_Reset() to get the*/ /* C6x into a known good state. */ /*--------------------------------------------------------------*/ OnRestart(int nErrorCode ) { /*------------------------------------------------------*/ /* Turn off L2 for all EMIFA CE spaces. App should */ /* manage these for coherancy in the application. */ /* GEL_TextOut("Turn off cache segment\n"); */ /*------------------------------------------------------*/ *(int *)0x01848200 = 0; // MAR0 *(int *)0x01848204 = 0; // MAR1 *(int *)0x01848208 = 0; // MAR2 *(int *)0x0184820c = 0; // MAR3 /*------------------------------------------------------*/ /* Disable EDMA events and interrupts and clear any */ /* pending events. */ /* GEL_TextOut("Disable EDMA event\n"); */ /*------------------------------------------------------*/ *(int *)0x01A0FFE8 = 0; // CIERL *(int *)0x01A0FFF4 = 0; // EERL *(int *)0x01A0FFF8 = 0xFFFFFFFF; // ECRL /* Disable other interrupts */ IER = 0; IFR = 0; } /*--------------------------------------------------------------*/ /* setup_memory_map() */ /* Memory map setup */ /*--------------------------------------------------------------*/ setup_memory_map() { GEL_MapOn(); GEL_MapReset(); /* On-chip memory map */ GEL_MapAdd(0x00000000, 0, 0x00030000, 1, 1); // Internal RAM (L2) mem GEL_MapAdd(0x01800000, 0, 0x00000024, 1, 1); // EMIF control regs GEL_MapAdd(0x01840000, 0, 0x00000004, 1, 1); // Cache configuration reg GEL_MapAdd(0x01844000, 0, 0x00000018, 1, 1); // L2 base addr & count regs GEL_MapAdd(0x01844020, 0, 0x00000018, 1, 1); // L1 base addr & count regs GEL_MapAdd(0x01845000, 0, 0x00000008, 1, 1); // L2 flush & clean regs GEL_MapAdd(0x01848200, 0, 0x00000010, 1, 1); // CE0 mem attribute regs GEL_MapAdd(0x01848240, 0, 0x00000010, 1, 1); // CE1 mem attribute regs GEL_MapAdd(0x01848280, 0, 0x00000010, 1, 1); // CE2 mem attribute regs GEL_MapAdd(0x018482c0, 0, 0x00000010, 1, 1); // CE3 mem attribute regs GEL_MapAdd(0x01880000, 0, 0x00000004, 1, 1); // HPI control reg GEL_MapAdd(0x018c0000, 0, 0x00000028, 1, 1); // McBSP0 regs GEL_MapAdd(0x01900000, 0, 0x00000028, 1, 1); // McBSP1 regs GEL_MapAdd(0x01940000, 0, 0x0000000c, 1, 1); // Timer0 regs GEL_MapAdd(0x01980000, 0, 0x0000000c, 1, 1); // Timer1 regs GEL_MapAdd(0x019c0000, 0, 0x0000000c, 1, 1); // Interrupt selector regs GEL_MapAdd(0x019c0200, 0, 0x00000004, 1, 1); // Device configuration GEL_MapAdd(0x01a00000, 0, 0x00000800, 1, 1); // EDMA parameter RAM GEL_MapAdd(0x01a0ff00, 0, 0x00000010, 1, 1); // EDMA event selector GEL_MapAdd(0x01a0ffe0, 0, 0x00000020, 1, 1); // EDMA control regs GEL_MapAdd(0x01b00000, 0, 0x00000028, 1, 1); // GPIO GEL_MapAdd(0x01b40000, 0, 0x0000003c, 1, 1); // I2C0 GEL_MapAdd(0x01b44000, 0, 0x0000003c, 1, 1); // I2C1 GEL_MapAdd(0x01b4c000, 0, 0x00000300, 1, 1); // McASP0 GEL_MapAdd(0x01b50000, 0, 0x00000300, 1, 1); // McASP1 GEL_MapAdd(0x01b7c000, 0, 0x00000128, 1, 1); // PLL GEL_MapAdd(0x01bc0000, 0, 0x00000050, 1, 1); // Emulation regs GEL_MapAdd(0x02000000, 0, 0x00000014, 0, 1); // QDMA regs GEL_MapAdd(0x02000020, 0, 0x00000014, 0, 1); // QDMA pseudo-regs GEL_MapAdd(0x30000000, 0, 0x04000000, 1, 1); // McBSP0 data GEL_MapAdd(0x34000000, 0, 0x04000000, 1, 1); // McBSP1 data GEL_MapAdd(0x3c000000, 0, 0x00010000, 1, 1); // McASP0 data GEL_MapAdd(0x3c100000, 0, 0x00010000, 1, 1); // McASP1 data /* Off-chip memory map */ GEL_MapAdd(0x80000000, 0, 0x00800000, 1, 1); // CE0, SDRAM, 8 MBytes GEL_MapAdd(0x90000000, 0, 0x00100000, 1, 1); // CE1, 16-bit ROM, 1MBytes GEL_MapAdd(0xA0000000, 0, 0x10000000, 1, 1); // CE2 - Daughtercard GEL_MapAdd(0xB0000000, 0, 0x10000000, 1, 1); // CE3 - Daughtercard } /*--------------------------------------------------------------*/ /* clear_memory_map() */ /* Memory map disable */ /*--------------------------------------------------------------*/ clear_memory_map() { GEL_MapOff(); } /*--------------------------------------------------------------*/ /* init_emif() */ /* Emif initialization */ /*--------------------------------------------------------------*/ init_emif() { #define EMIF_GCTL 0x01800000 #define EMIF_CE1 0x01800004 #define EMIF_CE0 0x01800008 #define EMIF_CE2 0x01800010 #define EMIF_CE3 0x01800014 #define EMIF_SDRAMCTL 0x01800018 #define EMIF_SDRAMTIM 0x0180001C #define EMIF_SDRAMEXT 0x01800020 #define EMIF_CCFG 0x01840000; // Cache configuration register /* EMIF setup */ *(int *)EMIF_GCTL = 0x00000068; *(int *)EMIF_CE0 = 0xffffff93; // CE0 SDRAM 16-bit // ff93 = 0b1111,1111,1001,0011 *(int *)EMIF_CE1 = 0x02208812; // CE1 Flash 16-bit *(int *)EMIF_CE2 = 0x22a28a22; // CE2 Daughtercard 32-bit async *(int *)EMIF_CE3 = 0x22a28a22; // CE3 Daughtercard 32-bit async *(int *)EMIF_SDRAMCTL = 0x57114000; // SDRAM control (8 Mb) // 0b0101,0111, 0001,0001, 0100,0000, 0000,0000 // tCK = 12.5ns @ 80MHz // tRC = 60ns = 5tCK => TRC = 5 - 1 = 4 // tRP = 15ns = 2tCK => TRP = 2 - 1 = 1 // tRCD = 15ns = 2tCK => TRCD = 2 - 1 = 1 // INIT = 1, RFEN = 1 // SDCSZ = 01(256), SDRSZ = 01(4K), SDBSZ = 1(4banks) *(int *)EMIF_SDRAMTIM = 0x000004E2; // SDRAM timing (refresh) // tREF = 64ms @ 4096rows => 15625ns = 1250 = 0x4E2 @ 1 row *(int *)EMIF_SDRAMEXT = 0x000a8529; // SDRAM Extension register // 0b0000,0000, 0000,1010, 1000,0101, 0010,0101 // TCL = 0 (CAS=2) // tRAS = 37ns = 3tCK => TRAS = 3 - 1 = 2 // tRRD = 14ns = 2tCK => TRRD = 0 // TWR = 2 - 1 = 1 // THZP = ? // RD2RD, RD2DEAC, RD2WR, R2WDQM, WR2WR, WR2DEAC, WR2RD GEL_TextOut("EMIF done.\n"); } /*--------------------------------------------------------------*/ /* flush_cache() */ /* Flush L1 & L2 cache */ /*--------------------------------------------------------------*/ flush_cache() { /* Invalidate L1P and L1D */ *(int *)0x01840000 = (*(int *)0x01840000 | 0x00000300); /* Clean L2 */ *(int *)0x01845004 = 0x1; } /*--------------------------------------------------------------*/ /* C6713 PLL SUPPORT */ /*--------------------------------------------------------------*/ #define PLL_BASE_ADDR 0x01b7c000 #define PLL_PID ( PLL_BASE_ADDR + 0x000 ) #define PLL_CSR ( PLL_BASE_ADDR + 0x100 ) #define PLL_MULT ( PLL_BASE_ADDR + 0x110 ) #define PLL_DIV0 ( PLL_BASE_ADDR + 0x114 ) #define PLL_DIV1 ( PLL_BASE_ADDR + 0x118 ) #define PLL_DIV2 ( PLL_BASE_ADDR + 0x11C ) #define PLL_DIV3 ( PLL_BASE_ADDR + 0x120 ) #define PLL_OSCDIV1 ( PLL_BASE_ADDR + 0x124 ) #define CSR_PLLEN 0x00000001 #define CSR_PLLPWRDN 0x00000002 #define CSR_PLLRST 0x00000008 #define CSR_PLLSTABLE 0x00000040 #define DIV_ENABLE 0x00008000 /*--------------------------------------------------------------*/ /* reset_pll() */ /* Pll Reset */ /*--------------------------------------------------------------*/ reset_pll() { /* Set the PLL back to power on reset state*/ *(int *)PLL_CSR = 0x00000048; *(int *)PLL_DIV3 = 0x00008001; *(int *)PLL_DIV2 = 0x00008001; *(int *)PLL_DIV1 = 0x00008000; *(int *)PLL_DIV0 = 0x00008000; *(int *)PLL_MULT = 0x00000007; *(int *)PLL_MULT = 0x00000007; *(int *)PLL_OSCDIV1 = 0x00080007; } /*--------------------------------------------------------------*/ /* init_pll() */ /* Pll Initialization */ /*--------------------------------------------------------------*/ init_pll() { /*------------------------------------------------------*/ /* When PLLEN is off DSP is running with CLKIN clock */ /* source, currently 50MHz or 20ns clk rate. */ /*------------------------------------------------------*/ *(int *)PLL_CSR &= ~CSR_PLLEN; /* Reset the pll. PLL takes 125ns to reset. */ *(int *)PLL_CSR |= CSR_PLLRST; /*------------------------------------------------------*/ /* PLLOUT = CLKIN/(DIV0+1) * PLLM */ /* 400 = 50/1 * 8 */ /*------------------------------------------------------*/ *(int *)PLL_DIV0 = DIV_ENABLE + 0; *(int *)PLL_MULT = 8; *(int *)PLL_OSCDIV1 = DIV_ENABLE + 4; /*------------------------------------------------------*/ /* Program in reverse order. */ /* DSP requires that pheriheral clocks be less then */ /* 1/2 the CPU clock at all times. */ /*------------------------------------------------------*/ *(int *)PLL_DIV3 = DIV_ENABLE + 4; *(int *)PLL_DIV2 = DIV_ENABLE + 3; *(int *)PLL_DIV1 = DIV_ENABLE + 1; *(int *)PLL_CSR &= ~CSR_PLLRST; /*------------------------------------------------------*/ /* Now enable pll path and we are off and running at */ /* 200MHz with 80 MHz SDRAM. */ /*------------------------------------------------------*/ *(int *)PLL_CSR |= CSR_PLLEN; GEL_TextOut("PLL done.\n"); } /*--------------------------------------------------------------*/ /* DSK6713 MENU */ /*--------------------------------------------------------------*/ menuitem "DSK6713 Functions"; hotmenu Reset() { GEL_Reset( ); } hotmenu InitEmif() { init_emif(); } hotmenu InitPll() { init_pll(); } /*--------------------------------------------------------------*/ /* RESET MENU */ /*--------------------------------------------------------------*/ menuitem "Resets"; hotmenu ClearBreakPts_Reset_EMIFset() { GEL_BreakPtReset(); GEL_Reset(); init_emif(); } hotmenu FlushCache() { flush_cache(); } hotmenu ResetPll() { reset_pll(); } /*--------------------------------------------------------------*/ /* MEMORY MAP MENU */ /*--------------------------------------------------------------*/ menuitem "Memory Map"; hotmenu SetMemoryMap() { setup_memory_map(); } hotmenu ClearMemoryMap() { clear_memory_map(); } /*--------------------------------------------------------------*/ /* Check DSK MENU */ /*--------------------------------------------------------------*/ menuitem "Check DSK"; hotmenu QuickTest() { GEL_TextOut("checking.. OK.\n\n"); }