;/*
; *  Copyright 2007 by Texas Instruments Japan Limited.
; *  All rights reserved. Property of Texas Instruments Japan Limited.
; *  You may modify the programs on the condition of using the programs
; *  solely and exclusively with semiconductor devices manufactured  by 
; *  or for TI.
; *  
; *  THE PROGRAMS ARE PROVIDED "AS IS". TIJ MAKES NO WARRANTIES OR
; *  REPRESENTATIONS, EITHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING ANY
; *  IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
; *  LACK OF VIRUSES, ACCURACY OR COMPLETENESS OF RESPONSES, RESULTS AND LACK OF
; *  NEGLIGENCE. TIJ DISCLAIMS ANY WARRANTY OF TITLE, QUIET ENJOYMENT, QUIET
; *  POSSESSION, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY
; *  RIGHTS WITH REGARD TO THE PROGRAMS OR YOUR USE OF THOSE PROGRAMS. 
; */


;**************************************************************
;* Define the Value of EMIF Conf Register
;*                NEED to customize these values.
;**************************************************************

;EMIFA Register Address and Values
EMIFA_ADDR          .equ  0x01800000  ;EMIFA Register Address
EMIFA_GCTL_V        .equ  0x00000068  ;EMIFA global control
EMIFA_CE0_V         .equ  0xffffff93  ;EMIFA CE1
EMIFA_CE1_V         .equ  0x02208812  ;EMIFA CE0
EMIFA_CE2_V         .equ  0x22a28a22  ;EMIFA CE2
EMIFA_CE3_V         .equ  0x22a28a22  ;EMIFA CE3
EMIFA_SDRAMCTL_V    .equ  0x57114000  ;EMIFA SDRAM control
EMIFA_SDRAMTIM_V    .equ  0x000004e2  ;SDRAM timing (refresh)
EMIFA_SDRAMEXT_V    .equ  0x000a8529  ;SDRAM extended control

;**************************************************************
;* Define COPY Table Address
;*                NEED to customize this value.
;**************************************************************

COPY_TABLE          .equ  0x90000400  ;depend on "-bootorg" option



;**************************************************************
;* BOOT PROGRAM
;**************************************************************
  .sect ".boot_load"      ;user section name
  .global _boot

_boot:
;**************************************************************
;* DEBUG LOOP -  COMMENT OUT B FOR NORMAL OPERATION
;**************************************************************
      zero  B1
_myloop:
  ;[!B1]  B  _myloop
      nop  5
_myloopend:  nop

;**************************************************************
;* CONFIGURE EMIF
;**************************************************************
;* Set EMIFA Reg. address to A4 *******************************
      mvkl  EMIFA_ADDR, A4
      mvkh  EMIFA_ADDR, A4
      
;* Configure params to EMIFA registers ************************
      mvkl  EMIFA_GCTL_V, B4
      mvkh  EMIFA_GCTL_V, B4
      stw   B4, *+A4[0]      ; set global control reg.

      mvkl  EMIFA_CE0_V, B4
      mvkh  EMIFA_CE0_V, B4
      stw   B4, *+A4[2]      ; set EMIFA CE0 reg.
      
      mvkl  EMIFA_CE1_V, B4
      mvkh  EMIFA_CE1_V, B4
      stw   B4, *+A4[1]      ; set EMIFA CE1 reg.
      
      mvkl  EMIFA_CE2_V, B4
      mvkh  EMIFA_CE2_V, B4
      stw   B4, *+A4[4]      ; set EMIFA CE2 reg.
      
      mvkl  EMIFA_CE3_V, B4
      mvkh  EMIFA_CE3_V, B4
      stw   B4, *+A4[5]      ; set EMIFA CE3 reg.
      
      mvkl  EMIFA_SDRAMCTL_V, B4
      mvkh  EMIFA_SDRAMCTL_V, B4
      stw   B4, *+A4[6]      ; set SDRAM timing reg.
      
      mvkl  EMIFA_SDRAMTIM_V, B4
      mvkh  EMIFA_SDRAMTIM_V, B4
      stw   B4, *+A4[7]      ; set SDRAM ext ctrl reg.
      
      mvkl  EMIFA_SDRAMEXT_V, B4
      mvkh  EMIFA_SDRAMEXT_V, B4
      stw   B4, *+A4[8]      ; set SDRAM control reg.
      
;**************************************************************
; Copy sections
;**************************************************************
_copy_section:
      mvkl  COPY_TABLE, A3    ; load table pointer
      mvkh  COPY_TABLE, A3
      
      ldw    *A3++, B1      ; read entry point
      
copy_section_top:
      ldw    *A3++, B0      ; read byte count of the section
      ldw    *A3++, A4      ; read destination start address
      nop    3

  [!b0]  b    copy_done      ; If section size=0, end copy
      nop    5          ; and jump to entry point
      
copy_loop:
      ldb    *A3++,B5      ; read data from ROM
      sub    B0, 1, B0      ; decrement counter
  [ b0]  b    copy_loop      ; coutinue copy till counter=0
  [!b0]  b    copy_section_top  ; jump to copy_section_top when copy is completed
      zero  A1
  [!b0]  and    3, A3, A1
      stb    B5, *A4++      ; write data to RAM
  [!b0]  and    -4, A3, A5      ; round address up to next multiple of 4
  [ a1]  add    4, A5, A3      ; round address up to next multiple of 4

;**************************************************************
; Jump to entry point
;**************************************************************
copy_done:
      b  .S2  B1          ; jump to _c_int00
      nop    5